diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-07 15:07:46 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-12 20:45:52 +0000 |
| commit | 79e61603dc1e7c335a3e3f9c1f70b135cd8cfb96 (patch) | |
| tree | e50e09e41b8b988b75dfaf1715d564f56a9137e6 | |
| parent | a3cd3066ba8176b61a0ae917105bf13b513232fa (diff) | |
soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces
PCH-S maps certain MMIO BARs differently than low power PCHs. The
reserved ranges taken from Intel DOC #630603.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/iomap.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index 9ff8f54d01..4f692422db 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -12,11 +12,19 @@ /* * Memory-mapped I/O registers. */ +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define PCH_PRESERVED_BASE_ADDRESS 0xfe000000 +#define PCH_PRESERVED_BASE_SIZE 0x00800000 + +#define PCH_TRACE_HUB_BASE_ADDRESS 0xfd800000 +#define PCH_TRACE_HUB_BASE_SIZE 0x00800000 +#else #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 #define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 +#endif #define UART_BASE_SIZE 0x1000 |