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| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-28 17:55:02 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-30 03:53:42 +0000 |
| commit | 063e933194ec9b41775f5e2f1a175f1c97657f1b (patch) | |
| tree | 152dc59e7f37a09ab9f81fa7950d1958ee8a150d /src/ec/google/chromeec/ec.c | |
| parent | e37e668e5a189e3344f9d6f1f89dce29f4fcd5f7 (diff) | |
soc/intel/skylake: Align PMC offset 0x31C name with CNL
As per EDS PMC BASE Offset 0x31C is known as CPPMVRIC hence rename
CIR31C with CPPMVRIC.
Change-Id: Idaff62fb742e6c58b1d8e662b5e4087fa2da79a3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45795
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/ec/google/chromeec/ec.c')
0 files changed, 0 insertions, 0 deletions