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authorMario Scheithauer <mario.scheithauer@siemens.com>2022-04-28 14:48:23 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-05-17 12:56:33 +0000
commit89c497b6d1aaaf0de399977279940d7c2bc00769 (patch)
tree32b36ab0ffab7151ec00a1841702f938f51f2250 /src/drivers/wwan/fm/chip.h
parent0a635ab1e875bc96c8c00221659f6e75b4e1db14 (diff)
mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
On this mainboard there are legacy PCI devices connected behind a PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This patch disables the unused PCI clock outputs on the XIO2001 bridge. Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/wwan/fm/chip.h')
0 files changed, 0 insertions, 0 deletions