diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2022-04-28 14:48:23 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-17 12:56:33 +0000 |
| commit | 89c497b6d1aaaf0de399977279940d7c2bc00769 (patch) | |
| tree | 32b36ab0ffab7151ec00a1841702f938f51f2250 /src | |
| parent | 0a635ab1e875bc96c8c00221659f6e75b4e1db14 (diff) | |
mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
On this mainboard there are legacy PCI devices connected behind a
PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This
patch disables the unused PCI clock outputs on the XIO2001 bridge.
Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c index 0dfd2d8a5a..36252a79a3 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -2,6 +2,7 @@ #include <baseboard/variants.h> #include <bootstate.h> +#include <device/pci_ids.h> #include <gpio.h> #include <intelblocks/pcr.h> #include <soc/gpio.h> @@ -9,9 +10,16 @@ void variant_mainboard_final(void) { + struct device *dev; + /* PIR8 register mapping for PCIe root ports INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */ pcr_write16(PID_ITSS, 0x3150, 0x1032); + + /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ + dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0); + if (dev) + pci_write_config8(dev, 0xd8, 0x3e); } static void finalize_boot(void *unused) |