diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-11-14 01:36:09 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-21 13:41:10 +0000 |
| commit | cbbfd68481002fd5b12e832f6b6c4bbd0fa671ad (patch) | |
| tree | 8c01fc9fe9eb13003bd5f55023895727e1b29cd8 /src/drivers/sil | |
| parent | 5578d912576a518175c8067b0ad88961b9032660 (diff) | |
soc/intel/mtl: Keep SOC_INTEL_COMMON_BASECODE_RAMTOP for non-ChromeOS
This patch guarantees that non-ChromeOS platforms continue to enable
early caching.
ChromeOS devices, on the other hand, control this configuration through
the motherboard configuration based on the underlying SoC.
BUG=b:306677879
TEST=Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for google/rex.
Change-Id: I412b2b6a807dc0f5f2632f0fbd56bd37689dead3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/drivers/sil')
0 files changed, 0 insertions, 0 deletions