diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-11-14 01:36:09 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-21 13:41:10 +0000 |
| commit | cbbfd68481002fd5b12e832f6b6c4bbd0fa671ad (patch) | |
| tree | 8c01fc9fe9eb13003bd5f55023895727e1b29cd8 | |
| parent | 5578d912576a518175c8067b0ad88961b9032660 (diff) | |
soc/intel/mtl: Keep SOC_INTEL_COMMON_BASECODE_RAMTOP for non-ChromeOS
This patch guarantees that non-ChromeOS platforms continue to enable
early caching.
ChromeOS devices, on the other hand, control this configuration through
the motherboard configuration based on the underlying SoC.
BUG=b:306677879
TEST=Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for google/rex.
Change-Id: I412b2b6a807dc0f5f2632f0fbd56bd37689dead3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 923a2b4283..e95756f35b 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -79,7 +79,7 @@ config SOC_INTEL_METEORLAKE select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BASECODE - select SOC_INTEL_COMMON_BASECODE_RAMTOP + select SOC_INTEL_COMMON_BASECODE_RAMTOP if !MAINBOARD_HAS_CHROMEOS select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 2c39bcd0f5..9534fc19ef 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -181,7 +181,8 @@ static void fill_tme_params(FSP_M_CONFIG *m_cfg) m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); if (!m_cfg->TmeEnable) return; - m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT); + m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT) && + CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP); if (m_cfg->GenerateNewTmeKey) { uint32_t ram_top = get_ramtop_addr(); if (!ram_top) { |