diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-23 15:07:49 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-29 20:18:43 +0000 |
| commit | 56e2d7d21aeffb75af34606bc034ee4fed560775 (patch) | |
| tree | d6c6ee8c465effb41697da412acaac4929adca60 /src/drivers/intel/fsp1_1/include/fsp | |
| parent | 73ac12196c61c8d0c21a54dfa87b858662d6859a (diff) | |
soc/intel/skylake: Use common cpu/intel/car romstage code
Setting up the console and entering postcar can be done in a common
place.
Change-Id: I8a8db0fcb4f0fbbb121a8195a8a8b6644c28db07
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32962
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/include/fsp')
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/car.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 0ae687a9d7..c05139231c 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -31,7 +31,6 @@ struct cache_as_ram_params { /* Entry points from the cache-as-ram assembly code. */ asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params); -asmlinkage void romstage_c_entry(void); /* Per stage calls from the above two functions. The void * return from * cache_as_ram_stage_main() is the stack pointer to use in RAM after * exiting cache-as-ram mode. */ |