diff options
| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2021-10-23 00:34:43 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-26 17:44:14 +0000 |
| commit | 02164027b2c9678bd4f5616e0ec34694da351a2c (patch) | |
| tree | 58a03e7367db7daca092ab28537ec2949a2c4db1 /src/cpu/x86/Kconfig | |
| parent | 71dfa82380a682d4e3214bd9e139b45fc3391dff (diff) | |
cpu/x86: Introduce and use `CPU_X86_LAPIC`
With using a Kconfig option to add the x86 LAPIC support code to the
build, there's no need for adding the corresponding directory to subdirs
in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added
(cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding
MTRR code selection patch and having verified that all platforms
added the MTRR code on that patch shows that soc/example/min86 and
soc/intel/quark are the only platforms that don't end up selecting the
LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y
which gets overridden to n in the Kconfig of the two SoCs mentioned
above.
Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/cpu/x86/Kconfig')
| -rw-r--r-- | src/cpu/x86/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index bae38891ad..a289325523 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -4,6 +4,10 @@ config CPU_X86_CACHE_HELPER help Add the x86_enable_cache ramstage helper function to the build. +config CPU_X86_LAPIC + bool + default y + config PARALLEL_MP def_bool y depends on !LEGACY_SMP_INIT |