diff options
33 files changed, 13 insertions, 31 deletions
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 5ee0f82fe3..003aa1f532 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -7,4 +7,3 @@ ramstage-y += chip_name.c ramstage-y += model_14_init.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/lapic diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 86d840bff2..a5914475e8 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -10,4 +10,3 @@ smm-y += udelay.c subdirs-y += ../../mtrr subdirs-y += ../../smm -subdirs-y += ../../../x86/lapic diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index 1cc8eff9b2..9464372d22 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -7,4 +7,3 @@ ramstage-y += chip_name.c ramstage-y += model_16_init.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/lapic diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index f2263d042e..51f90ef6e9 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -8,4 +8,3 @@ ramstage-y += model_16_init.c ramstage-y += update_microcode.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/lapic diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index ec0ceea06d..b425efd5d6 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -15,7 +15,6 @@ bootblock-y += bootblock.c postcar-y += ../car/non-evict/exit_car.S -subdirs-y += ../../x86/lapic subdirs-y += ../microcode subdirs-y += ../turbo diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index fb85bdf4d5..b676eb6a77 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -1,6 +1,5 @@ ramstage-y += model_2065x_init.c subdirs-y += ../../x86/name -subdirs-y += ../../x86/lapic subdirs-y += ../../intel/turbo subdirs-y += ../../intel/microcode subdirs-y += ../smm/gen1 diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index fec509c193..90dfeb3a66 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -2,7 +2,6 @@ ramstage-y += model_206ax_init.c subdirs-y += ../../x86/name subdirs-y += ../smm/gen1 -subdirs-y += ../../x86/lapic subdirs-y += ../microcode subdirs-y += ../turbo diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index b2422f4957..856ecf6697 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -7,7 +7,6 @@ subdirs-y += ../model_65x subdirs-y += ../model_67x subdirs-y += ../model_68x subdirs-y += ../model_6bx -subdirs-y += ../../x86/lapic subdirs-y += ../microcode bootblock-y += ../car/p3/cache_as_ram.S diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index e338ea1836..58ec230d18 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_106cx -subdirs-y += ../../x86/lapic subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 5f92919e17..8cafa7e65a 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_1067x -subdirs-y += ../../x86/lapic subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 48ba3a95a2..f6d54c9f8a 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_106cx -subdirs-y += ../../x86/lapic subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 520016808f..9b08be6cf6 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -2,7 +2,6 @@ subdirs-y += ../model_6fx subdirs-y += ../model_f3x subdirs-y += ../model_f4x subdirs-y += ../model_1067x -subdirs-y += ../../x86/lapic subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index 42e18060b2..b50dee5ccc 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -6,5 +6,3 @@ bootblock-y += bootblock.c romstage-y += ../intel/car/romstage.c ramstage-y += qemu.c - -subdirs-y += ../x86/lapic diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index bae38891ad..a289325523 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -4,6 +4,10 @@ config CPU_X86_CACHE_HELPER help Add the x86_enable_cache ramstage helper function to the build. +config CPU_X86_LAPIC + bool + default y + config PARALLEL_MP def_bool y depends on !LEGACY_SMP_INIT diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 05df6e0f92..a6c51d023a 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,4 +1,5 @@ subdirs-$(CONFIG_CPU_X86_CACHE_HELPER) += cache +subdirs-$(CONFIG_CPU_X86_LAPIC) += lapic subdirs-y += mtrr subdirs-y += pae subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 5e6b257029..87874418c3 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -2,8 +2,6 @@ ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) -subdirs-y += ../../../cpu/x86/lapic - subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage # Beware that all-y also adds the compilation unit to verstage on PSP diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e3eab29e35..45e9c80330 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -2,7 +2,6 @@ ifeq ($(CONFIG_SOC_AMD_PICASSO),y) -subdirs-y += ../../../cpu/x86/lapic subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 4a126d8e2d..fd3ebf7a66 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) subdirs-y += ../../../cpu/amd/mtrr/ -subdirs-y += ../../../cpu/x86/lapic bootblock-y += uart.c bootblock-y += BiosCallOuts.c diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig index 660bf369e7..560f2200f6 100644 --- a/src/soc/example/min86/Kconfig +++ b/src/soc/example/min86/Kconfig @@ -19,6 +19,10 @@ config SOC_SPECIFIC_OPTIONS select NO_MMCONF_SUPPORT select UNKNOWN_TSC_RATE +config CPU_X86_LAPIC + bool + default n + config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld default 0x100 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index bd554b995a..d857e8b59b 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -2,7 +2,6 @@ ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3a723dcbb3..a557d1ea40 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic bootblock-y += bootblock/bootblock.c bootblock-y += ../common/block/cpu/pm_timer_emulation.c diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 33aaba0d8f..2bd558d5da 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 07bd26fe26..4ecb4e79f1 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index bc15e1f025..3c8bf5798a 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_BASE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/intel/common bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 3fdff0d197..5d9b32773b 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_INTEL_DENVERTON_NS),y) subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic bootblock-y += bootblock/bootblock.c bootblock-y += spi.c diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index c32ba1f245..3ac46ef2b2 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_ELKHARTLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 847418de1c..90c3036a8b 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_ICELAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 276f3c0cd5..d718dd875f 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 1a9bfef942..bf9d475cd5 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -24,6 +24,10 @@ config CPU_SPECIFIC_OPTIONS select USE_MARCH_586 select NO_SMM +config CPU_X86_LAPIC + bool + default n + ##### # Debug serial output # The following options configure the debug serial port diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 775bec1ce6..ea96caada7 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic bootblock-y += bootblock/bootblock.c bootblock-y += i2c.c diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 9e5a3c8231..6da5e00713 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index ef38ce8acc..0cd267b712 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) subdirs-y += ../../../../cpu/intel/turbo -subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/intel/microcode romstage-y += romstage.c ddr.c diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index b0714d4ef7..f7599a34c1 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y) subdirs-y += ../../../../cpu/intel/microcode subdirs-y += ../../../../cpu/intel/turbo -subdirs-y += ../../../../cpu/x86/lapic postcar-y += soc_util.c |