diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-04 14:23:54 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-09 09:56:06 +0000 |
| commit | 4513020064cc4765e723f6f3cc2b8a45a0dc6545 (patch) | |
| tree | e9b31b8b64518a62f6a7885a1de54171471c918b /src/cpu/intel | |
| parent | 907bd5d44e574227baa1f5b3c00b31b8dc351096 (diff) | |
cpu/intel: Use the common code to initialize the romstage timestamps
The initial timestamps are now pushed on the stack when entering the
romstage C code.
Tested on Asus P5QC.
Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/romstage.c | 3 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 3 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 2daf47b29b..264ad4ab7f 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -17,6 +17,7 @@ #include <cpu/x86/mtrr.h> #include <arch/symbols.h> #include <program_loading.h> +#include <timestamp.h> #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000 @@ -59,6 +60,8 @@ static void romstage_main(unsigned long bist) */ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { + timestamp_init(base_timestamp); + timestamp_add_now(TS_START_ROMSTAGE); romstage_main(bist); } #endif diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 688f3579db..ff729d6285 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -77,9 +77,6 @@ void romstage_common(const struct romstage_params *params) int boot_mode; int wake_from_s3; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (params->bist == 0) enable_lapic(); |