From 4513020064cc4765e723f6f3cc2b8a45a0dc6545 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 4 Jan 2019 14:23:54 +0100 Subject: cpu/intel: Use the common code to initialize the romstage timestamps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/cpu/intel/car/romstage.c | 3 +++ src/cpu/intel/haswell/romstage.c | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 2daf47b29b..264ad4ab7f 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -17,6 +17,7 @@ #include #include #include +#include #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000 @@ -59,6 +60,8 @@ static void romstage_main(unsigned long bist) */ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { + timestamp_init(base_timestamp); + timestamp_add_now(TS_START_ROMSTAGE); romstage_main(bist); } #endif diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 688f3579db..ff729d6285 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -77,9 +77,6 @@ void romstage_common(const struct romstage_params *params) int boot_mode; int wake_from_s3; - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (params->bist == 0) enable_lapic(); -- cgit v1.2.3