intel/fsp_rangeley: Load BSP microcode in bootblock

Load microcode to BSP in bootblock so later on the FSP TempRamInit call
will return with success. The updated fsp1_0 driver calls TempRamInit
API with dummy microcode, so FSP will not handle the microcode load. If
BSP is not loaded with microcode before calling TempRamInit API, the
call will fail with error No Valid Microcode Was Found.

Change-Id: I9c55acaf3353a759bb0119f0a5402a704ffb2c4a
Signed-off-by: David Guckian <david.guckian@intel.com>
Reviewed-on: http://review.coreboot.org/12367
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: York Yang <york.yang@intel.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c
index ab9bcffaee..edbbe1b362 100644
--- a/src/cpu/intel/fsp_model_406dx/bootblock.c
+++ b/src/cpu/intel/fsp_model_406dx/bootblock.c
@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <cpu/x86/cache.h>
+#include <cpu/intel/microcode/microcode.c>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
@@ -86,6 +87,10 @@ static void bootblock_cpu_init(void)
 {
 	/* Check for Warm Reset */
 	check_for_warm_reset();
+
+	/* Load microcode before any caching. */
+	intel_update_microcode_from_cbfs();
+
 	enable_rom_caching();
 	set_no_evict_mode_msr();
 }