diff options
| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-04 22:21:15 -0600 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-13 01:28:36 +0100 |
| commit | 66e0c4c8c46eec6063a7bb8933990cc5c203ec2e (patch) | |
| tree | 6e4e497d1e245f6e0bac3f2d100ce4f4e8aa0747 /src/cpu/intel/fsp_model_206ax/Kconfig | |
| parent | 580d11f1f1448a618c339d60b83b52f3bd259b8d (diff) | |
cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS
CPU_MICROCODE_IN_CBFS was designed to mean that loading microcode updates
from a CBFS file is supported, however, the name implies that microcode is
present in CBFS. This has recently caused confusion both with contributions
from Google, as well as SAGE. Rename this option to
SUPPORT_CPU_UCODE_IN_CBFS in order to make it clearer that what is meant is
"hey, the code we have for this CPU supports loading microcode updates from
CBFS", and prevent further confusion.
Change-Id: I394555f690b5ab4cac6fbd3ddbcb740ab1138339
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4482
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/intel/fsp_model_206ax/Kconfig')
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/Kconfig | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index dbff6e01e0..6a008bf3b2 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -32,7 +32,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select CPU_MICROCODE_IN_CBFS if HAVE_FSP_BIN + select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select TSC_SYNC_MFENCE config BOOTBLOCK_CPU_INIT @@ -53,12 +53,12 @@ config ENABLE_VMX config CPU_MICROCODE_CBFS_LOC hex - depends on CPU_MICROCODE_IN_CBFS + depends on SUPPORT_CPU_UCODE_IN_CBFS default 0xfff70000 config CPU_MICROCODE_CBFS_LEN hex - depends on CPU_MICROCODE_IN_CBFS + depends on SUPPORT_CPU_UCODE_IN_CBFS default 0xC000 if CPU_INTEL_FSP_MODEL_306AX default 0x2800 if CPU_INTEL_FSP_MODEL_206AX |