diff options
| -rw-r--r-- | src/cpu/Kconfig | 7 | ||||
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/Kconfig | 6 | ||||
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/microcode_blob.c | 2 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/Kconfig | 2 | ||||
| -rw-r--r-- | src/cpu/intel/microcode/microcode.c | 8 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/Kconfig | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/Kconfig | 2 | ||||
| -rw-r--r-- | src/cpu/via/nano/Kconfig | 2 | ||||
| -rw-r--r-- | src/include/cpu/intel/microcode.h | 2 |
9 files changed, 16 insertions, 17 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6c118b7908..cd6c7a0d4f 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -73,7 +73,7 @@ config SSE2 endif # ARCH_X86 -config CPU_MICROCODE_IN_CBFS +config SUPPORT_CPU_UCODE_IN_CBFS bool default n @@ -90,9 +90,8 @@ config CPU_MICROCODE_ADDED_DURING_BUILD choice prompt "Include CPU microcode in CBFS" if ARCH_X86 - default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS - default CPU_MICROCODE_CBFS_EXTERNAL if CPU_MICROCODE_IN_CBFS - default CPU_MICROCODE_CBFS_NONE + default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS + default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS config CPU_MICROCODE_CBFS_GENERATE bool "Generate from tree" diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index dbff6e01e0..6a008bf3b2 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -32,7 +32,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select CPU_MICROCODE_IN_CBFS if HAVE_FSP_BIN + select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select TSC_SYNC_MFENCE config BOOTBLOCK_CPU_INIT @@ -53,12 +53,12 @@ config ENABLE_VMX config CPU_MICROCODE_CBFS_LOC hex - depends on CPU_MICROCODE_IN_CBFS + depends on SUPPORT_CPU_UCODE_IN_CBFS default 0xfff70000 config CPU_MICROCODE_CBFS_LEN hex - depends on CPU_MICROCODE_IN_CBFS + depends on SUPPORT_CPU_UCODE_IN_CBFS default 0xC000 if CPU_INTEL_FSP_MODEL_306AX default 0x2800 if CPU_INTEL_FSP_MODEL_206AX diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c index 8bd790ade4..309ea75fa1 100644 --- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c +++ b/src/cpu/intel/fsp_model_206ax/microcode_blob.c @@ -18,7 +18,7 @@ */ unsigned microcode[] = { -#if IS_ENABLED(CONFIG_CPU_MICROCODE_IN_CBFS) +#if IS_ENABLED(SUPPORT_CPU_UCODE_IN_CBFS) #include "microcode_blob.h" #endif }; diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 7b6fc43257..03c3518b41 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -14,7 +14,7 @@ config CPU_SPECIFIC_OPTIONS select SMM_MODULES select RELOCATABLE_MODULES select DYNAMIC_CBMEM - select CPU_MICROCODE_IN_CBFS + select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 1991ed8472..a68b24d180 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -30,11 +30,11 @@ #include <cpu/intel/microcode.h> #ifdef __PRE_RAM__ -#if CONFIG_CPU_MICROCODE_IN_CBFS +#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS #include <arch/cbfs.h> #endif #else -#if CONFIG_CPU_MICROCODE_IN_CBFS +#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS #include <cbfs.h> #endif #include <smp/spinlock.h> @@ -82,7 +82,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_CPU_MICROCODE_IN_CBFS +#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS #define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" @@ -192,7 +192,7 @@ void intel_update_microcode_from_cbfs(void) #endif } -#else /* !CONFIG_CPU_MICROCODE_IN_CBFS */ +#else /* !CONFIG_SUPPORT_CPU_UCODE_IN_CBFS */ void intel_update_microcode(const void *microcode_updates) { diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index b0f4e65031..9040ebcf0b 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select SMM_TSEG select HAVE_INIT_TIMER - select CPU_MICROCODE_IN_CBFS + select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 5b3f893943..426e613c9c 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select CPU_MICROCODE_IN_CBFS + select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index 3b1c2137e8..674c0f3f0c 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -28,7 +28,7 @@ config CPU_SPECIFIC_OPTIONS select MMX select SSE2 select CACHE_AS_RAM - select CPU_MICROCODE_IN_CBFS + select SUPPORT_CPU_UCODE_IN_CBFS config DCACHE_RAM_BASE hex diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 9e4773e847..460bafb6fc 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_CPU_MICROCODE_IN_CBFS +#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); /* Find a microcode that matches the revision and platform family returning * NULL if none found. */ |