diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-03 17:14:19 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-13 15:12:38 +0000 |
| commit | 348b79f05733d1186ccd3b03a990fa4694885e7e (patch) | |
| tree | 62deaa7c1f341d8f3b73cc6cd2289c7ee3c6d5ab /src/cpu/intel/car/p4-netburst | |
| parent | 995b99d9963e0ada5ef46d45a50ebefdb9dd090a (diff) | |
cpu/intel/car: Align the stack to 16 bytes before romstage_main
Change-Id: I1415c18779bc481fdec5f72f83c06a58ce6d5c39
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26797
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/car/p4-netburst')
| -rw-r--r-- | src/cpu/intel/car/p4-netburst/cache_as_ram.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 95ecba96bd..60423967a5 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -355,6 +355,10 @@ skip_cache_rom: /* Setup the stack. */ movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp + /* Align the stack 16 bytes */ + andl $0xfffffff0, %esp + /* Account for pushing the BIST result */ + subl $12, %esp /* Restore the BIST result. */ movl %ebp, %eax |