diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-21 20:06:10 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-21 20:06:10 +0000 |
| commit | 9839cbd53fdcfcee52c406d9f52af924192e618d (patch) | |
| tree | a38daaa0b545aaf36a7ad5f5df9dfe73e08d97da /src/cpu/amd/model_lx/cache_as_ram.inc | |
| parent | cf036d1266d7ec307aac437105b094acbc9681ec (diff) | |
* clean up all but two warnings on artecgroup dbe61
* integrate vsm init into normal x86.c code (so it can run above 1M)
* call void main(unsigned long bist) except void cache_as_ram_main(void)
on Geode LX (as we do on almost all other platforms now)
* Unify Geode LX MSR setup (will bring most non-working LX targets back
to life)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/model_lx/cache_as_ram.inc')
| -rw-r--r-- | src/cpu/amd/model_lx/cache_as_ram.inc | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc index 096a96155d..f776a7a727 100644 --- a/src/cpu/amd/model_lx/cache_as_ram.inc +++ b/src/cpu/amd/model_lx/cache_as_ram.inc @@ -34,6 +34,8 @@ /** /***************************************************************************/ DCacheSetup: + /* Save the BIST result */ + movl %eax, %ebx invd /* set cache properties */ @@ -173,9 +175,17 @@ DCacheSetupBad: hlt /* issues */ jmp DCacheSetupBad DCacheSetupGood: - /* Go do early init and memory setup */ - call cache_as_ram_main + + /* Restore the BIST result */ + movl %ebx, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call romstage.c main function */ + call main done_cache_as_ram_main: /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ |