diff options
| author | Li-Ta Lo <ollie@lanl.gov> | 2006-04-13 17:00:38 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2006-04-13 17:00:38 +0000 |
| commit | d8d8fffa0edc8b86f1efab2f3a44c9d53cefe556 (patch) | |
| tree | 7ac60db80a99217f17f7148c7a93490054dbe0ac /src/cpu/amd/model_gx2/cpubug.c | |
| parent | cf648c9a99c59f25400f198b99de2f92e57db349 (diff) | |
minor modification
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/model_gx2/cpubug.c')
| -rw-r--r-- | src/cpu/amd/model_gx2/cpubug.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c index 9b008e627c..3c51208938 100644 --- a/src/cpu/amd/model_gx2/cpubug.c +++ b/src/cpu/amd/model_gx2/cpubug.c @@ -229,7 +229,9 @@ CPUbugIAENG2900 ENDP #endif } -void bug118253(void){ +void bug118253(void) +{ + /* GLPCI PIO Post Control shouldn't be enabled */ msr_t msr; msr = rdmsr(GLPCI_SPARE); @@ -289,14 +291,13 @@ void bug118339(void) msr.lo = 0x80004000; wrmsr(msrnum, msr); - /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */ - /* As per Todd Roberts in PBz1094 and PBz1095 */ - /* Moved from CPUREG to CPUBUG per Tom Sylla */ + /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */ + /* As per Todd Roberts in PBz1094 and PBz1095 */ + /* Moved from CPUREG to CPUBUG per Tom Sylla */ msrnum = 0x04C000042; /* GLCP SETMCTL Register */; msr = rdmsr(msrnum); - msr.hi |= 8; /* Bit 35 = MCP_IN */ + msr.hi |= 8; /* Bit 35 = MCP_IN */ wrmsr(msrnum, msr); - } |