diff options
| author | Li-Ta Lo <ollie@lanl.gov> | 2006-04-13 17:00:38 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2006-04-13 17:00:38 +0000 |
| commit | d8d8fffa0edc8b86f1efab2f3a44c9d53cefe556 (patch) | |
| tree | 7ac60db80a99217f17f7148c7a93490054dbe0ac /src/cpu | |
| parent | cf648c9a99c59f25400f198b99de2f92e57db349 (diff) | |
minor modification
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/model_gx2/cpubug.c | 13 | ||||
| -rw-r--r-- | src/cpu/amd/model_gx2/cpureginit.c | 5 | ||||
| -rw-r--r-- | src/cpu/amd/model_gx2/vsmsetup.c | 16 |
3 files changed, 20 insertions, 14 deletions
diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c index 9b008e627c..3c51208938 100644 --- a/src/cpu/amd/model_gx2/cpubug.c +++ b/src/cpu/amd/model_gx2/cpubug.c @@ -229,7 +229,9 @@ CPUbugIAENG2900 ENDP #endif } -void bug118253(void){ +void bug118253(void) +{ + /* GLPCI PIO Post Control shouldn't be enabled */ msr_t msr; msr = rdmsr(GLPCI_SPARE); @@ -289,14 +291,13 @@ void bug118339(void) msr.lo = 0x80004000; wrmsr(msrnum, msr); - /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */ - /* As per Todd Roberts in PBz1094 and PBz1095 */ - /* Moved from CPUREG to CPUBUG per Tom Sylla */ + /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */ + /* As per Todd Roberts in PBz1094 and PBz1095 */ + /* Moved from CPUREG to CPUBUG per Tom Sylla */ msrnum = 0x04C000042; /* GLCP SETMCTL Register */; msr = rdmsr(msrnum); - msr.hi |= 8; /* Bit 35 = MCP_IN */ + msr.hi |= 8; /* Bit 35 = MCP_IN */ wrmsr(msrnum, msr); - } diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c index e50079955e..51fbe2ae87 100644 --- a/src/cpu/amd/model_gx2/cpureginit.c +++ b/src/cpu/amd/model_gx2/cpureginit.c @@ -169,13 +169,14 @@ cpuRegInit (void){ /* */ /* FooGlue Setup*/ /* */ +#if 0 /* Enable CIS mode B in FooGlue*/ msrnum = MSR_FG + 0x10; msr = rdmsr(msrnum); msr.lo &= ~3; msr.lo |= 2; /* ModeB*/ wrmsr(msrnum, msr); - +#endif /* */ /* Disable DOT PLL. Graphics init will enable it if needed.*/ @@ -209,7 +210,7 @@ cpuRegInit (void){ /* I hate to put this check here but it doesn't really work in cpubug.asm*/ msrnum = MSR_GLCP+0x17; msr = rdmsr(msrnum); - if (msr.lo < CPU_REV_2_1){ + if (msr.lo >= CPU_REV_2_1){ msrnum = CPU_PF_BTB_CONF; msr = rdmsr(msrnum); msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET; diff --git a/src/cpu/amd/model_gx2/vsmsetup.c b/src/cpu/amd/model_gx2/vsmsetup.c index 593c7f716b..b462fcd8fd 100644 --- a/src/cpu/amd/model_gx2/vsmsetup.c +++ b/src/cpu/amd/model_gx2/vsmsetup.c @@ -195,8 +195,8 @@ static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm) /* Dump zeros in the other segregs */ " mov %ax, %es \n" /* FixMe: Big real mode for gs, fs? */ - //" mov %ax, %fs \n" - //" mov %ax, %gs \n" + " mov %ax, %fs \n" + " mov %ax, %gs \n" " mov $0x40, %ax \n" " mov %ax, %ds \n" //" mov %cx, %ax \n" @@ -277,8 +277,8 @@ void do_vsmbios(void) memcpy((void *) 0x60000, buf, size); - for (i = 0; i < 0x800000; i++) - outb(0xaa, 0x80); + //for (i = 0; i < 0x800000; i++) + // outb(0xaa, 0x80); /* ecx gets smm, edx gets sysm */ printk_err("Call real_mode_switch_call_vsm\n"); @@ -568,8 +568,6 @@ void setup_realmode_idt(void) idts[1].cs = 0; idts[1].offset = 16384; memcpy(16384, &debughandle, &end_debughandle - &debughandle); - - } @@ -745,6 +743,12 @@ int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp, case 0x5f0f: *eax=0x860f; break; + case 0xBEA7: + *eax=33; + break; + case 0xBEA4: + *eax=333; + break; } return res; } |