diff options
| author | Kerry Sheh <shekairui@gmail.com> | 2012-02-07 20:31:35 +0800 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2012-02-16 19:26:32 +0100 |
| commit | d3e990c6e5124f30b394f5dbd4902ea8bf341b07 (patch) | |
| tree | c5667f18c6b406a0350e43db4f760ca97174f98d /src/cpu/amd/agesa/family15/Kconfig | |
| parent | 53c1d204ed134017e9a04d68f175bb7f6c6e0915 (diff) | |
AGESA F15: AGESA family15 model 00-0fh cpu wrapper
Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/555
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/cpu/amd/agesa/family15/Kconfig')
| -rw-r--r-- | src/cpu/amd/agesa/family15/Kconfig | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig new file mode 100644 index 0000000000..0f2f920256 --- /dev/null +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -0,0 +1,82 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_AGESA_FAMILY15 + bool + select PCI_IO_CFG_EXT + select AMD_AGESA + +if CPU_AMD_AGESA_FAMILY15 + +config CPU_AMD_SOCKET_G34 + bool + default n + help + AMD G34 Socket + +config CPU_AMD_SOCKET_C32 + bool + default n + help + AMD C32 Socket + +config CPU_AMD_SOCKET_AM3R2 + bool + default n + help + AMD AM3r2 Socket + +config EXT_RT_TBL_SUPPORT + bool + default n + +config EXT_CONF_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_BASE + hex + default 0xfff80000 + +config XIP_ROM_SIZE + hex + default 0x80000 + +config HAVE_INIT_TIMER + bool + default y + +config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + depends on CPU_AMD_AGESA_FAMILY15 + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD AGESA code. + +endif #CPU_AMD_AGESA_FAMILY15 |