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authorArthur Heymans <arthur@aheymans.xyz>2022-07-13 07:20:47 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-07-14 23:10:30 +0000
commitefd2720e4790924a434823d701664de8ee2eb9e4 (patch)
tree5103e33858ebfbdb00a5cf44bb4a285e3bf6f627 /src/arch/x86/include
parent84b2f9f5b8e40eb9a114c1be5741b4141c5566e0 (diff)
arch/x86: Mark prepare_and_run_postcar noreturn
This moves the die() statement to a common place. Change-Id: I24c9f00bfee169b4ca57b469c089188ec62ddada Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/arch/x86/include')
-rw-r--r--src/arch/x86/include/arch/romstage.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h
index d637d19b8a..063d4edd6b 100644
--- a/src/arch/x86/include/arch/romstage.h
+++ b/src/arch/x86/include/arch/romstage.h
@@ -43,7 +43,7 @@ void fill_postcar_frame(struct postcar_frame *pcf);
* prepare_and_run_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use.
*/
-void prepare_and_run_postcar(void);
+void __noreturn prepare_and_run_postcar(void);
/*
* Systems without a native coreboot cache-as-ram teardown may implement