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authorPatrick Rudolph <patrick.rudolph@9elements.com>2024-03-13 16:43:09 +0100
committerPatrick Rudolph <patrick.rudolph@9elements.com>2024-03-19 10:18:21 +0000
commit49fe84e2c2f83fb2b31900c6bcafb2631aeb46de (patch)
treebec219623c3fc1190042c1912c90877f835f1d5b /payloads/linuxcheck/linuxcheck.h
parent8061957cc12769714e7041093c065c6d6d212249 (diff)
soc/intel/xeon_sp/spr: Enable 512 MMCONF buses by default
As of now coreboot only supported one PCI segment group and thus the MMCONF size had to be limited to 256 buses on ibm/sbp1. Since the default FSP doesn't allow to disable unused IIO stacks a patched version had to be used. Those unused IIO stacks consume lots of PCI bus ranges, leaving no free buses for the secondary side behind PCI bridges. The IIO disable mechanism doesn't work after ACPI G3 exit and thus requires multiple reboots when the previous state was G3. Since coreboot now supports multi PCI segment groups enable 512 MMCONF buses on 4S platforms by default and drop the IIO stack disable UPDs on ibm/sbp1. This allows to boot faster without the need for a patched FSP. The use of multiple PCI segment groups might prevent legacy software from working properly, however the only board where multiple PCI segment groups are used uses u-root as default payload. TEST=Booted on ibm/sbp1 to ubuntu22.04 using two PCI segment groups. TEST=intel/archercity CRB Change-Id: I4e6e5eca1196d4ab50e43b4b58d24eca444ab519 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'payloads/linuxcheck/linuxcheck.h')
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