diff options
| -rw-r--r-- | src/mainboard/ibm/sbp1/romstage.c | 20 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 29 |
3 files changed, 30 insertions, 20 deletions
diff --git a/src/mainboard/ibm/sbp1/romstage.c b/src/mainboard/ibm/sbp1/romstage.c index 5cda689162..365d6b10ae 100644 --- a/src/mainboard/ibm/sbp1/romstage.c +++ b/src/mainboard/ibm/sbp1/romstage.c @@ -270,8 +270,6 @@ static const UINT8 sbp1_socket_config_iou[CONFIG_MAX_SOCKET][5] = { void mainboard_memory_init_params(FSPM_UPD *mupd) { - UINT32 *sktbmp; - /* Set Rank Margin Tool to disable. */ mupd->FspmConfig.EnableRMT = 0x0; @@ -287,25 +285,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) else mupd->FspmConfig.serialDebugMsgLvl = 0; - /* Force 256MiB MMCONF (Segment0) only */ - mupd->FspmConfig.mmCfgSize = 0x2; mupd->FspmConfig.PcieHotPlugEnable = 1; - - /* - * Disable unused IIO stack: - * Socket 0 : IIO1, IIO4 - * Socket 1 : IIO1, IIO2 - * Socket 2 : IIO1, IIO5 - * Socket 3 : IIO1, IIO5 - * Stack Disable bit mapping is: - * IIO stack number: 1 2 3 4 5 - * Stack Disable Bit: 1 5 3 2 4 - */ - sktbmp = (UINT32 *)&mupd->FspmConfig.StackDisableBitMap[0]; - sktbmp[0] = BIT(1) | BIT(2); - sktbmp[1] = BIT(1) | BIT(5); - sktbmp[2] = BIT(1) | BIT(4); - sktbmp[3] = BIT(1) | BIT(4); soc_config_iio(mupd, sbp1_socket_config, sbp1_socket_config_iou); } diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 52aaec1797..923527e36c 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -89,6 +89,7 @@ config ECAM_MMCONF_BASE_ADDRESS default 0x80000000 config ECAM_MMCONF_BUS_NUMBER + default 512 if MAX_SOCKET = 4 default 256 config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 4cce21f249..74976b362e 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -211,6 +211,35 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) m_cfg->mmiohBase = 0x2000; m_cfg->mmiohSize = 0x3; + /* + * By default FSP will set MMCFG size to 256 buses on 1S and 2S platforms + * and 512 buses on 4S platforms. 512 buses are implemented by using multiple + * PCI segment groups and is likely incompatible with legacy software stacks. + */ + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { + case 2048: + m_cfg->mmCfgSize = 5; + break; + case 1024: + m_cfg->mmCfgSize = 4; + break; + case 512: + m_cfg->mmCfgSize = 3; + break; + case 256: + m_cfg->mmCfgSize = 2; + break; + case 128: + m_cfg->mmCfgSize = 1; + break; + case 64: + m_cfg->mmCfgSize = 0; + break; + default: + printk(BIOS_ERR, "%s: Unsupported ECAM_MMCONF_BUS_NUMBER = %d\n", + __func__, CONFIG_ECAM_MMCONF_BUS_NUMBER); + } + m_cfg->BoardTypeBitmask = 0x11111133; /* |