soc/intel/meteorlake: Update CSE firmware status registers

The patch updates HFSTS4, HFSTS5 & HFSTS6 register definitions as per
MTL Intel CSME BIOS Specification (doc# 729124). Also, the patch logs
the firmware status details as per the new register definition.

TEST=Build and boot the coreboot on Rex

Snippet from coreboot log with the patch:
	[DEBUG]  ME: CPU Debug Disabled          : NO
	[DEBUG]  ME: TXT Support                 : NO

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ibee9a0955efc22ea0d9fdbba2d09e57d8851e22e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69577
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions