diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2021-10-21 10:40:23 +0200 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-22 14:56:18 +0000 |
commit | b2a442ed5915e17b057efcfb81b5c826cafd63f3 (patch) | |
tree | 27033adfe8376189b644597adb26ecb02cb72972 /configs/config.google_meep_cros | |
parent | 37e261f3741458c4ac774975912196de5d05178e (diff) |
soc/intel/cannonlake: Fix PEG1 _PRT generation
Some weird things happen inside FSP and the routing is not correctly
applied, with PIN D being used but lacking a proper routing in ACPI.
To work around this issue generate _PRT for all 4 INT pins.
Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'configs/config.google_meep_cros')
0 files changed, 0 insertions, 0 deletions