diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-10-21 10:40:23 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-22 14:56:18 +0000 |
| commit | b2a442ed5915e17b057efcfb81b5c826cafd63f3 (patch) | |
| tree | 27033adfe8376189b644597adb26ecb02cb72972 | |
| parent | 37e261f3741458c4ac774975912196de5d05178e (diff) | |
soc/intel/cannonlake: Fix PEG1 _PRT generation
Some weird things happen inside FSP and the routing is not correctly
applied, with PIN D being used but lacking a proper routing in ACPI.
To work around this issue generate _PRT for all 4 INT pins.
Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index f22e39d442..32c5cbb8c6 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -44,6 +44,12 @@ static const struct slot_irq_constraints irq_constraints[] = { FIXED_INT_PIRQ(SA_DEVFN_PEG0, PCI_INT_A, PIRQ_A), FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_B, PIRQ_B), FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_C, PIRQ_C), + /* + * It looks like FSP does not apply this mapping properly to + * the PEG functions. The PINx to PIRQx mapping needs to be there + * in ACPI however in case PIN D is used. + */ + FIXED_INT_PIRQ(PCI_DEVFN(SA_DEV_SLOT_PEG, 3), PCI_INT_D, PIRQ_D), }, }, { |