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authorMichael Niewöhner <foss@mniewoehner.de>2021-09-15 16:40:35 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-09-23 06:32:11 +0000
commit9abeb9c0626244e5f889536bbc9de0bf685eb922 (patch)
treec80ef03d5c4b029cc5222eb69c92448d7dd27b93 /README.md
parent46ef53621265feeeebca475a0078f6bd301fcb35 (diff)
soc/intel/tgl: correct wrong gpio GPI enable register base offset
Reference: Intel doc# 631120-001. Change-Id: Iaf3a1b7bc38a1b30f8cc901bd6496e77f2d92cfd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
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