diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-15 16:40:35 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-23 06:32:11 +0000 |
| commit | 9abeb9c0626244e5f889536bbc9de0bf685eb922 (patch) | |
| tree | c80ef03d5c4b029cc5222eb69c92448d7dd27b93 | |
| parent | 46ef53621265feeeebca475a0078f6bd301fcb35 (diff) | |
soc/intel/tgl: correct wrong gpio GPI enable register base offset
Reference: Intel doc# 631120-001.
Change-Id: Iaf3a1b7bc38a1b30f8cc901bd6496e77f2d92cfd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/gpio_defs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h index c90931d80c..2f404393a0 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h @@ -289,7 +289,7 @@ #define GPE_DW_MASK 0xfff00 #define HOSTSW_OWN_REG_0 0xb0 #define GPI_INT_STS_0 0x100 -#define GPI_INT_EN_0 0x110 +#define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define GPI_NMI_STS_0 0x1c0 |