soc/mediatek/mt8196: Enable MMU operation for L2C SRAM and DMA

- Turn off L2C SRAM and reconfigure as L2 cache:
  Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
  After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
  the L2C SRAM as L2 cache.

- Configure DMA buffer in DRAM:
  Set DRAM DMA to be non-cacheable to load blob correctly.

TEST=build pass, register(disable_l2c) read ok
BUG=b:317009620

Change-Id: I6a3cb63d3418f085f5d8d08b282dd59ea431c294
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83925
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

0 files changed, 0 insertions, 0 deletions