diff options
| author | V Sowmya <v.sowmya@intel.com> | 2021-06-21 09:50:47 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-08 15:50:57 +0000 |
| commit | d5ab16308667c5772e56f5345ea5fc68f7343a92 (patch) | |
| tree | 2fca1f709065fdb56fcfd609c2c22ef65d4de448 | |
| parent | 590eb2bb9c9fac5d3a7d3526601108efe23d801b (diff) | |
mb/google/brya0: Update the FIVR configurations
This patch sets the disable the external voltage rails since brya
board doesn't have V1p05 and Vnn bypass rails implemented.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/brya0/overridetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 9ef74787ad..9584b277b1 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -36,6 +36,12 @@ chip soc/intel/alderlake register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn + # bypass rails implemented. + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf |