diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-11 16:49:02 +0100 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-14 08:19:01 +0000 |
| commit | a3495c0d7b249ce5cf53335d2036e31f1a86739c (patch) | |
| tree | 3fd6249fba7d3067074dcb60f9f3370c5776cfb7 | |
| parent | 70d8baef921c50a49e055de3ed32cca618820c11 (diff) | |
soc/intel/tigerlake: Drop unreferenced devicetree settings
No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: I5f5da8dfcec7dd35981611830b555cab5d6af3e3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48572
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 5c124de492..fe10d0dbcb 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -263,10 +263,8 @@ struct soc_intel_tigerlake_config { uint8_t SmbusEnable; /* Gfx related */ - uint8_t IgdDvmt50PreAlloc; uint8_t SkipExtGfxScan; - uint32_t GraphicsConfigPtr; uint8_t Device4Enable; /* HeciEnabled decides the state of Heci1 at end of boot |