diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2023-07-04 10:23:58 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-05 12:54:13 +0000 |
| commit | 8d0a063810136672b3c27fbd092afc654951bf1b (patch) | |
| tree | 6eddcb02fb8671aa593022241ee07aa7b00fbe8c | |
| parent | 969a2a9a30a2d2c0ec855b832ea32b706fb4b4b2 (diff) | |
soc/intel/meteorlake: Set TCC to 90°C
Set tcc_offset value to 20 in chipset for Thermal Control
Circuit (TCC) activation feature for meteorlake silicon.
Also, remove tcc_offset default value from rex baseboard
and variants.
BUG=b:270664854
BRANCH=None
TEST=Build FW and test on rex board
Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/screebo/overridetree.cb | 3 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/chipset.cb | 3 |
3 files changed, 3 insertions, 6 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 76b9dcd82a..1b37784bcd 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -36,9 +36,6 @@ chip soc/intel/meteorlake # DPTF enable register "dptf_enable" = "1" - # Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20) - register "tcc_offset" = "20" - # Enable CNVi BT register "cnvi_bt_core" = "true" diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index c43c09f0fb..1cc0530db8 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -64,9 +64,6 @@ chip soc/intel/meteorlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - # Temporary setting TCC of 90C = Tj max - Tcc - register "tcc_offset" = "20" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 1f68eff5e7..59eb2c96d6 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -19,6 +19,9 @@ chip soc/intel/meteorlake # putting it under register "common_soc_config" in overridetree.cb file. register "common_soc_config.pch_thermal_trip" = "130" + # Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20) + register "tcc_offset" = "20" + # Enable CNVi WiFi register "cnvi_wifi_core" = "true" |