From 8d0a063810136672b3c27fbd092afc654951bf1b Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Tue, 4 Jul 2023 10:23:58 +0530 Subject: =?UTF-8?q?soc/intel/meteorlake:=20Set=20TCC=20to=2090=C2=B0C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set tcc_offset value to 20 in chipset for Thermal Control Circuit (TCC) activation feature for meteorlake silicon. Also, remove tcc_offset default value from rex baseboard and variants. BUG=b:270664854 BRANCH=None TEST=Build FW and test on rex board Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9 Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Eric Lai Reviewed-by: Subrata Banik --- src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 3 --- src/mainboard/google/rex/variants/screebo/overridetree.cb | 3 --- src/soc/intel/meteorlake/chipset.cb | 3 +++ 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 76b9dcd82a..1b37784bcd 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -36,9 +36,6 @@ chip soc/intel/meteorlake # DPTF enable register "dptf_enable" = "1" - # Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20) - register "tcc_offset" = "20" - # Enable CNVi BT register "cnvi_bt_core" = "true" diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index c43c09f0fb..1cc0530db8 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -64,9 +64,6 @@ chip soc/intel/meteorlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - # Temporary setting TCC of 90C = Tj max - Tcc - register "tcc_offset" = "20" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 1f68eff5e7..59eb2c96d6 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -19,6 +19,9 @@ chip soc/intel/meteorlake # putting it under register "common_soc_config" in overridetree.cb file. register "common_soc_config.pch_thermal_trip" = "130" + # Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20) + register "tcc_offset" = "20" + # Enable CNVi WiFi register "cnvi_wifi_core" = "true" -- cgit v1.2.3