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authorZheng Bao <fishbaozi@gmail.com>2022-02-11 11:51:26 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-02-12 16:36:07 +0000
commit6c5ec8e31ccbe3d9bbf201c956fc3b54703a9767 (patch)
tree27868a5ff056213860377d27671485914f4fe0e9
parent39cf79900fa333992eb2614f7559dd1b2c7ac5e9 (diff)
amdfwtool: Add options to support mainboard specific SPL table
For the generic board which uses Cezanne, we use the generic SPL table. For the Guybrush Chromebook, we need to use a customized SPL file. BUG=b:216096562 Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
-rw-r--r--util/amdfwtool/amdfwtool.c8
-rw-r--r--util/amdfwtool/amdfwtool.h1
-rw-r--r--util/amdfwtool/data_parse.c8
3 files changed, 15 insertions, 2 deletions
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 1d5db12543..e586748b13 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -642,6 +642,7 @@ static void free_psp_firmware_filenames(amd_fw_entry *fw_table)
if (index->filename &&
index->type != AMD_FW_VERSTAGE_SIG &&
index->type != AMD_FW_PSP_VERSTAGE &&
+ index->type != AMD_FW_SPL &&
index->type != AMD_FW_PSP_WHITELIST) {
free(index->filename);
}
@@ -1086,6 +1087,7 @@ enum {
AMDFW_OPT_USE_PSPSECUREOS,
AMDFW_OPT_LOAD_MP2FW,
AMDFW_OPT_LOAD_S0I3,
+ AMDFW_OPT_SPL_TABLE,
AMDFW_OPT_VERSTAGE,
AMDFW_OPT_VERSTAGE_SIG,
@@ -1131,6 +1133,7 @@ static struct option long_options[] = {
{"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS },
{"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW },
{"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 },
+ {"spl-table", required_argument, 0, AMDFW_OPT_SPL_TABLE },
{"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE },
{"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG },
/* BIOS Directory Table items */
@@ -1463,6 +1466,11 @@ int main(int argc, char **argv)
case AMDFW_OPT_LOAD_S0I3:
cb_config.s0i3 = true;
break;
+ case AMDFW_OPT_SPL_TABLE:
+ register_fw_filename(AMD_FW_SPL, sub, optarg);
+ sub = instance = 0;
+ cb_config.have_mb_spl = true;
+ break;
case AMDFW_OPT_WHITELIST:
register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg);
sub = instance = 0;
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index b14a437baf..79e52fc932 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -251,6 +251,7 @@ typedef struct _amd_cb_config {
bool load_mp2_fw;
bool multi_level;
bool s0i3;
+ bool have_mb_spl;
} amd_cb_config;
void register_fw_fuse(char *str);
diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c
index 6814346263..106ea65b69 100644
--- a/util/amdfwtool/data_parse.c
+++ b/util/amdfwtool/data_parse.c
@@ -283,8 +283,12 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
fw_type = AMD_FW_KEYDB_TOS;
subprog = 0;
} else if (strcmp(fw_name, "SPL_TABLE_FILE") == 0) {
- fw_type = AMD_FW_SPL;
- subprog = 0;
+ if (cb_config->have_mb_spl) {
+ fw_type = AMD_FW_SPL;
+ subprog = 0;
+ } else {
+ fw_type = AMD_FW_SKIP;
+ }
} else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) {
fw_type = AMD_FW_DMCU_ERAM;
subprog = 0;