diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-03-23 21:35:32 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-11 05:58:49 +0000 |
| commit | 3a077965dedfc757d05ee88561012981da591677 (patch) | |
| tree | 9eadb955c6337415119acbd33860e0417132b8e6 | |
| parent | 901578518fd40ec3c1ebbeef7d4f30e4bf7e663f (diff) | |
amd/fam15tn/gcccar.inc: Fix msr access with clang
Change-Id: I21bebd475dce373a77626d2e78a0ab10678ea8b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/gcccar.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index 5a0c1c458b..fb49c17c59 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -971,9 +971,9 @@ fam15_skipClearingBit4: 1: #.if (al == 01h) # TN only #Enable MSRC001_001F[EnableCf8ExtCfg] mov $NB_CFG, %ecx # MSR:C001_001F - _rdmsr + _RDMSR bts $(ENABLE_CF8_EXT_CFG - 32), %edx - _wrmsr + _WRMSR # Set F3x44[6, CpuErrDis] = 1 MAKE_EXT_PCI_ADDR 0, 0, 24, FUNC_3, 0x44 //MCA_NB_CFG //mov $(1 << 31 | 2 << 28 | (((MCA_NB_CFG) & (0x0F00)) >> 8) << 24 | 2 << 16 | 1 << 11 | FUNC_3 << 8), %eax |