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| author | Rob Barnes <robbarnes@google.com> | 2021-12-10 14:28:21 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-14 16:03:40 +0000 |
| commit | 3437a6fbb0f6d61a692a0c0b82c45b77e27ead8e (patch) | |
| tree | ceea4704857ba8f0082a8a1ee788b3577a3892af | |
| parent | 941239d54d972f23c42dc47d19801e2dc4957063 (diff) | |
soc/amd/{cezanne,common}: Add PSP_S0I3_RESUME_VERSTAGE Kconfig option
Add PSP_S0I3_RESUME_VERSTAGE Kconfig option. When enabled, verstage will
be run in PSP during S0i3 resume. Setting softfuse bit 40 enables this
in PSP.
BUG=b:200578885, b:202397678
BRANCH=None
TEST=Verstage runs during s0i3 resume on Nipperkin
Change-Id: I2c185f787c1e77bd09f6cbbb1f47deb665ed0c79
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/psp_verstage/Kconfig | 11 |
2 files changed, 13 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 58df7406ed..a05da8dc76 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -110,6 +110,10 @@ else PSP_SOFTFUSE_BITS += 29 endif +ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) +PSP_SOFTFUSE_BITS += 40 +endif + # Use additional Soft Fuse bits specified in Kconfig PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig index 6cac8b70ed..45a5d22423 100644 --- a/src/soc/amd/common/psp_verstage/Kconfig +++ b/src/soc/amd/common/psp_verstage/Kconfig @@ -6,10 +6,17 @@ config PSP_VERSTAGE_CCP_DMA accessing the boot device. Select it on platforms which supports using CCP DMA to access the boot device. +config PSP_S0I3_RESUME_VERSTAGE + bool "S0i3 resume verstage" + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + default n + help + Select this item to enable running verstage during S0i3 resume. + config PSP_INIT_TPM_ON_S0I3_RESUME bool - depends on TPM2 && VBOOT_STARTS_BEFORE_BOOTBLOCK - default VBOOT_STARTS_BEFORE_BOOTBLOCK + depends on TPM2 && PSP_S0I3_RESUME_VERSTAGE + default PSP_S0I3_RESUME_VERSTAGE help If the TPM is reset while in S0i3, it must be reinitialized during s0i3 resume. This must be performed in PSP verstage since |