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authorSean Rhodes <sean@starlabs.systems>2021-11-23 08:13:38 +0000
committerFelix Held <felix-coreboot@felixheld.de>2021-12-13 23:47:23 +0000
commit941239d54d972f23c42dc47d19801e2dc4957063 (patch)
treeb89ff71aeb6903c91354e6b2b3c5bf6c58740968
parentf79f775eda71b66f9ca540f3a31e221cb269b5d6 (diff)
Documentation/releases: Update 4.16 release notes
* Add StarBook Mk V as new mainboard * Add option to disable Intel Management Engine via HECI Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9675a6a8960d93ae6de285d8b25ffc48a763483e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--Documentation/releases/coreboot-4.16-relnotes.md7
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/releases/coreboot-4.16-relnotes.md b/Documentation/releases/coreboot-4.16-relnotes.md
index a4c7af28f9..83b2760287 100644
--- a/Documentation/releases/coreboot-4.16-relnotes.md
+++ b/Documentation/releases/coreboot-4.16-relnotes.md
@@ -17,3 +17,10 @@ Significant changes
-------------------
### Add significant changes here
+
+### Option to disable Intel Management Engine
+Disable the Intel (CS)Management Engine via HECI based on Intel Core processors
+from Skylake to Alderlake. State is set baed on a cmos value of `me_state`. A
+value of `0` will result in a (CS)ME state of `0` (working) and value of `1`
+will result in a (CS)ME state of `3` (disabled). For an example cmos layout and
+more info, see [cse.c](../../src/soc/intel/common/block/cse/cse.c).