diff options
| author | Saurabh Mishra <mishra.saurabh@intel.com> | 2024-05-13 14:49:15 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-05-16 11:29:40 +0000 |
| commit | 1b2fe88a049e9f82264e007272f6fb66a31785b9 (patch) | |
| tree | 36d3e6cd643e0ac4e9107cf16f07ee3dc51a9f20 | |
| parent | 3d4128299f87681b82a1485fa116ed59680eca97 (diff) | |
include/device/pci_ids.h: Update TWL device IDs
Set lowercase hex format for IGD DIDs.
BUG=b:326901448
TEST=Build tivviks and verify the IGD IDs.
Change-Id: I1299512d1c48eba854fea2ec394cef40d44a87d7
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82414
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
| -rw-r--r-- | src/include/device/pci_ids.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index dd32f3308c..267cb3221f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4182,8 +4182,8 @@ #define PCI_DID_INTEL_RPL_U_GT4 0xa7ac #define PCI_DID_INTEL_RPL_U_GT5 0xa7ad #define PCI_DID_INTEL_LNL_M_GT2 0x64a0 -#define PCI_DID_INTEL_TWL_GT1_1 0x46D3 -#define PCI_DID_INTEL_TWL_GT1_2 0x46D4 +#define PCI_DID_INTEL_TWL_GT1_1 0x46d3 +#define PCI_DID_INTEL_TWL_GT1_2 0x46d4 #define PCI_DID_INTEL_PTL_GT2 0x64a0 /* Intel Northbridge Ids */ |