From 1b2fe88a049e9f82264e007272f6fb66a31785b9 Mon Sep 17 00:00:00 2001
From: Saurabh Mishra <mishra.saurabh@intel.com>
Date: Mon, 13 May 2024 14:49:15 +0530
Subject: include/device/pci_ids.h: Update TWL device IDs

Set lowercase hex format for IGD DIDs.

BUG=b:326901448
TEST=Build tivviks and verify the IGD IDs.

Change-Id: I1299512d1c48eba854fea2ec394cef40d44a87d7
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82414
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
---
 src/include/device/pci_ids.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index dd32f3308c..267cb3221f 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4182,8 +4182,8 @@
 #define PCI_DID_INTEL_RPL_U_GT4				0xa7ac
 #define PCI_DID_INTEL_RPL_U_GT5				0xa7ad
 #define PCI_DID_INTEL_LNL_M_GT2				0x64a0
-#define PCI_DID_INTEL_TWL_GT1_1				0x46D3
-#define PCI_DID_INTEL_TWL_GT1_2				0x46D4
+#define PCI_DID_INTEL_TWL_GT1_1				0x46d3
+#define PCI_DID_INTEL_TWL_GT1_2				0x46d4
 #define PCI_DID_INTEL_PTL_GT2				0x64a0
 
 /* Intel Northbridge Ids */
-- 
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