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| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-09 10:54:57 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-10 19:00:17 +0000 |
| commit | f87427f1a4303d6cab26f29641831b4d3dec8451 (patch) | |
| tree | c1878b2ea1ba29a4c87065c9172b97656ee186b3 /.gitreview | |
| parent | 78452a584a7f2c201a6e9917c034b42f6fed89c6 (diff) | |
soc/amd/stoneyridge: Add SPI registers
This is a copy/paste of amdblocks/lpc.h. The registers are different for
picasso and cezanne, so I'm moving them to soc.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to '.gitreview')
0 files changed, 0 insertions, 0 deletions