diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-09 10:54:57 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-10 19:00:17 +0000 |
| commit | f87427f1a4303d6cab26f29641831b4d3dec8451 (patch) | |
| tree | c1878b2ea1ba29a4c87065c9172b97656ee186b3 | |
| parent | 78452a584a7f2c201a6e9917c034b42f6fed89c6 (diff) | |
soc/amd/stoneyridge: Add SPI registers
This is a copy/paste of amdblocks/lpc.h. The registers are different for
picasso and cezanne, so I'm moving them to soc.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/lpc.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/lpc.h b/src/soc/amd/stoneyridge/include/soc/lpc.h new file mode 100644 index 0000000000..55e39cce90 --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/lpc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_STONEYRIDGE_LPC_H +#define AMD_STONEYRIDGE_LPC_H + +#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(6) +#define SPI_BASE_RESERVED (BIT(4) | BIT(5)) +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ABORT_ENABLE BIT(2) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_ROM_ALT_ENABLE BIT(0) +#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +#endif /* AMD_STONEYRIDGE_LPC_H */ |