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@@ -1,4 +1,6 @@ -This document describes known methods of flashing BIOS on Lenovo ThinkPads without external programmer. The main goal is flashing coreboot while running stock BIOS, but it may be used for flashing modified vendor BIOS as well. +This document describes known methods of flashing BIOS on Lenovo ThinkPads +without external programmer. The main goal is flashing coreboot while running +stock BIOS, but it may be used for flashing modified vendor BIOS as well. # Table of Contents @@ -22,25 +24,36 @@ This document describes known methods of flashing BIOS on Lenovo ThinkPads witho # Ivy Bridge series (X230, T430, etc.) -Old versions of stock BIOS for these models have several security issues. In context of this guide, two of them are of interest. +Old versions of stock BIOS for these models have several security issues. In +context of this guide, two of them are of interest. -**First** is the fact the SMM_BWP and BLE are not enabled in BIOS versions released before 2014. I have tested many versions on T430 and X230 and found out that SMM_BWP=1 only since the update, the changelog of which contains following line: +**First** is the fact the SMM_BWP and BLE are not enabled in BIOS versions +released before 2014. I have tested many versions on T430 and X230 and found out +that SMM_BWP=1 only since the update, the changelog of which contains following +line: > (New) Improved the UEFI BIOS security feature. -**Second** is [S3 Boot Script vulnerability](https://support.lenovo.com/eg/ru/product_security/s3_boot_protect), that was discovered and fixed later. +**Second** is [S3 Boot Script vulnerability](https://support.lenovo.com/eg/ru/product_security/s3_boot_protect), +that was discovered and fixed later. ## Requirements -- USB drive (in case you need to downgrade BIOS). There were reports that GPT-partitioned drive didn't work and the fix was to change partition table to MBR. +- USB drive (in case you need to downgrade BIOS). There were reports that + GPT-partitioned drive didn't work and the fix was to change partition table to + MBR. - Linux install that (can be) loaded in UEFI mode. - [CHIPSEC](https://github.com/chipsec/chipsec) -- Recent [flashrom](https://flashrom.org). At least version 1.0 is required, older versions of flashrom do not have `--ifd` option. (Workaround by using layout file is possible, but it's more complicated.) +- Recent [flashrom](https://flashrom.org). At least version 1.0 is required, + older versions of flashrom do not have `--ifd` option. (Workaround by using + layout file is possible, but it's more complicated.) - `iomem=relaxed` kernel parameter for using internal programmer. ## BIOS versions -Below is a table of BIOS versions that are vulnerable enough for our goals, per model. The version number means that you need to downgrade to that or earlier version. +Below is a table of BIOS versions that are vulnerable enough for our goals, per +model. The version number means that you need to downgrade to that or earlier +version. | Model | BIOS version | |------------|--------------| @@ -51,13 +64,21 @@ Below is a table of BIOS versions that are vulnerable enough for our goals, per | T530 | 2.60 | | W530 | 2.58 | -If your BIOS version is equal or lower, skip to the **[Examining protections](#examining-protections-theory)** section. If not, go through the downgrade process, described next. +If your BIOS version is equal or lower, skip to the +**[Examining protections](#examining-protections-theory)** section. If not, go +through the downgrade process, described next. ## Downgrading BIOS -Go to the Lenovo web site and download BIOS Update Bootable CD for your machine of needed version (see above). +Go to the Lenovo web site and download BIOS Update Bootable CD for your machine +of needed version (see above). -Lenovo states that BIOS has "security rollback prevention", meaning once you update it to some version X, you will not be able to downgrade it to pre-X version. That's not true. It seems that this is completely client-side restriction in flashing utilities (both Windows utility and Bootable CD). You just need to call `winflash.exe` or `dosflash.exe` directly. Therefore you need to modify the bootable CD image you just downloaded. +Lenovo states that BIOS has "security rollback prevention", meaning once you +update it to some version X, you will not be able to downgrade it to pre-X +version. That's not true. It seems that this is completely client-side +restriction in flashing utilities (both Windows utility and Bootable CD). You +just need to call `winflash.exe` or `dosflash.exe` directly. Therefore you need +to modify the bootable CD image you just downloaded. Extract an El Torito image: ``` @@ -73,11 +94,13 @@ ls /mnt ls /mnt/FLASH ``` -Inside the `FLASH` directory, there should be a directory called `G1ET93WW` or similar (exact name depends on your ThinkPad model). See what's inside: +Inside the `FLASH` directory, there should be a directory called `G1ET93WW` or +similar (exact name depends on your ThinkPad model). See what's inside: ``` ls /mnt/FLASH/G1ET93WW ``` -There must be a file with `.FL1` extension called `$01D2000.FL1` or something similar. +There must be a file with `.FL1` extension called `$01D2000.FL1` or something +similar. Now open the `AUTOEXEC.BAT` file: ``` @@ -90,7 +113,8 @@ PROMPT $p$g cd c:\flash command.com ``` -Replace the last line (`command.com`) with this (change path to the `.FL1` file according to yours): +Replace the last line (`command.com`) with this (change path to the `.FL1` file +according to yours): ``` dosflash.exe /sd /file G1ET93WW\$01D2000.FL1 ``` @@ -100,21 +124,25 @@ Save the file, then unmount the partition: sudo unmount /mnt ``` -Write this image to a USB drive (replace `/dev/sdX` with your USB drive device name): +Write this image to a USB drive (replace `/dev/sdX` with your USB drive device +name): ``` sudo dd if=./bios.img of=/dev/sdX bs=1M ``` -Now reboot and press F1 to enter BIOS settings. Open the **Startup** tab and set the startup mode to **Legacy** (or **Both**/**Legacy First**): +Now reboot and press F1 to enter BIOS settings. Open the **Startup** tab and set +the startup mode to **Legacy** (or **Both**/**Legacy First**): <a href="/screenshots/bios-legacy-only.jpg"><img src="/screenshots/bios-legacy-only.jpg" width="250px" /></a> <a href="/screenshots/bios-legacy-first.jpg"><img src="/screenshots/bios-legacy-first.jpg" width="250px" /></a> Press F10 to save changes and reboot. -Now, before you process, make sure that AC adapter is connected! If your battery will die during the process, you'll likely need external programmer to recover. +Now, before you process, make sure that AC adapter is connected! If your battery +will die during the process, you'll likely need external programmer to recover. -Boot from the USB drive (press F12 to select boot device), and BIOS flashing process should begin: +Boot from the USB drive (press F12 to select boot device), and BIOS flashing +process should begin: <a href="/screenshots/flashing1.jpg"><img src="/screenshots/flashing1.jpg" width="250px" /></a> <a href="/screenshots/flashing2.jpg"><img src="/screenshots/flashing2.jpg" width="250px" /></a> @@ -123,27 +151,41 @@ It may reboot a couple of times in the process. Do not interrupt it. #### Enabling UEFI mode -When downgrade is completed, go back to the BIOS settings and set startup mode to **UEFI** (or **Both**/**UEFI First**). This is required for vulnerability exploitation. +When downgrade is completed, go back to the BIOS settings and set startup mode +to **UEFI** (or **Both**/**UEFI First**). This is required for vulnerability +exploitation. <a href="/screenshots/bios-uefi-only.jpg"><img src="/screenshots/bios-uefi-only.jpg" width="250px" /></a> <a href="/screenshots/bios-uefi-first.jpg"><img src="/screenshots/bios-uefi-first.jpg" width="250px" /></a> -Then boot to your system and make sure that `/sys/firmware/efi` or `/sys/firmware/efivars` exist. +Then boot to your system and make sure that `/sys/firmware/efi` or +`/sys/firmware/efivars` exist. ## Examining protections (theory) There are two main ways that Intel platform provides to protect BIOS chip: -- **BIOS_CNTL** register of LPC Interface Bridge Registers (accessible via PCI configuration space, offset 0xDC). It has: - * **SMM_BWP** (*SMM BIOS Write Protect*) bit. If set to 1, the BIOS is writable only in SMM. Once set to 1, cannot be changed anymore. - * **BLE** (*BIOS Lock Enable*) bit. If set to 1, setting BIOSWE to 1 will raise SMI. Once set to 1, cannot be changed anymore. - * **BIOSWE** (*BIOS Write Enable*) bit. Controls whether BIOS is writable. This bit is always R/W. -- SPI Protected Range Registers (**PR0**-**PR4**) of SPI Configuration Registers (SPIBAR+0x74 - SPIBAR+0x84). Each register has bits that define protected range, plus WP bit, that defines whether write protection is enabled. - - There's also **FLOCKDN** bit of HSFS register (SPIBAR+0x04) of SPI Configuration Registers. When set to 1, PR0-PR4 registers cannot be written. Once set to 1, cannot be changed anymore. - -To be able to flash, we need SMM_BWP=0, BIOSWE=1, BLE=0, FLOCKDN=0 or SPI protected ranges (PRx) to have a WP bit set to 0. - -Let's see what we have. Make sure that you have [enabled and booted in UEFI mode](#enabling-uefi-mode), then examine HSFS register: +- **BIOS_CNTL** register of LPC Interface Bridge Registers (accessible via PCI + configuration space, offset 0xDC). It has: + * **SMM_BWP** (*SMM BIOS Write Protect*) bit. If set to 1, the BIOS is + writable only in SMM. Once set to 1, cannot be changed anymore. + * **BLE** (*BIOS Lock Enable*) bit. If set to 1, setting BIOSWE to 1 will + raise SMI. Once set to 1, cannot be changed anymore. + * **BIOSWE** (*BIOS Write Enable*) bit. Controls whether BIOS is writable. + This bit is always R/W. +- SPI Protected Range Registers (**PR0**-**PR4**) of SPI Configuration Registers + (SPIBAR+0x74 - SPIBAR+0x84). Each register has bits that define protected + range, plus WP bit, that defines whether write protection is enabled. + + There's also **FLOCKDN** bit of HSFS register (SPIBAR+0x04) of SPI + Configuration Registers. When set to 1, PR0-PR4 registers cannot be written. + Once set to 1, cannot be changed anymore. + +To be able to flash, we need SMM_BWP=0, BIOSWE=1, BLE=0, FLOCKDN=0 or SPI +protected ranges (PRx) to have a WP bit set to 0. + +Let's see what we have. Make sure that you have +[enabled and booted in UEFI mode](#enabling-uefi-mode), then examine HSFS +register: ``` sudo chipsec_main -m chipsec.modules.common.spi_lock ``` @@ -201,22 +243,27 @@ Other way to examine SPI configuration registers is to just dump SPIBAR: sudo chipsec_util mmio dump SPIBAR ``` -You will see SPIBAR address (0xFED1F800) and registers (for example, 00000004 is HSFS): +You will see SPIBAR address (0xFED1F800) and registers (for example, 00000004 is +HSFS): ``` [mmio] MMIO register range [0x00000000FED1F800:0x00000000FED1F800+00000200]: +00000000: 0BFF0500 +00000004: 0004E009 ... ``` -As you can see, the only thing we need is to unset WP bit on PR0-PR4. But that cannot be done once FLOCKDN is set to 1. +As you can see, the only thing we need is to unset WP bit on PR0-PR4. But that +cannot be done once FLOCKDN is set to 1. Now the fun part! -FLOCKDN may only be cleared by a hardware reset, which includes S3 state. On S3 resume boot path, the chipset configuration has to be restored and it's done by executing so-called S3 Boot Scripts. You can dump these scripts by executing: +FLOCKDN may only be cleared by a hardware reset, which includes S3 state. On S3 +resume boot path, the chipset configuration has to be restored and it's done by +executing so-called S3 Boot Scripts. You can dump these scripts by executing: ``` sudo chipsec_util uefi s3bootscript ``` -There are many entries. Along them, you can find instructions to write to HSFS (remember, we know that SPIBAR is 0xFED1F800): +There are many entries. Along them, you can find instructions to write to HSFS +(remember, we know that SPIBAR is 0xFED1F800): ``` Entry at offset 0x2B8F (len = 0x17, header len = 0x0): Data: @@ -229,13 +276,18 @@ Decoded: Count : 0x1 Values : 0x0004E009 ``` -These scripts are stored in memory. The vulnerability is that we can overwrite this memory, change these instructions and they will be executed on S3 resume. Once we patch that instruction to not set FLOCKDN bit, we will be able to write to PR0-PR4 registers. +These scripts are stored in memory. The vulnerability is that we can overwrite +this memory, change these instructions and they will be executed on S3 resume. +Once we patch that instruction to not set FLOCKDN bit, we will be able to write +to PR0-PR4 registers. ## Creating a backup -Before you proceed, please create a backup of the `bios` region. Then, in case something goes wrong, you'll be able to flash it back externally. +Before you proceed, please create a backup of the `bios` region. Then, in case +something goes wrong, you'll be able to flash it back externally. -The `me` region is locked due to active ME, so an attempt to create a full dump will fail. But you can back up the `bios`: +The `me` region is locked due to active ME, so an attempt to create a full dump +will fail. But you can back up the `bios`: ``` sudo flashrom -p internal -r bios_backup.rom --ifd -i bios ``` @@ -245,10 +297,13 @@ If you will even need to flash it back, use `--ifd -i bios` as well: ``` sudo flashrom -p <YOUR_PROGRAMMER> -w bios_backup.rom --ifd -i bios ``` -**Important:** if you will omit `--ifd -i bios` for flashing, you will brick your machine, because your backup has `FF`s in place of `fd` and `me` regions. Flash only `bios` region! +**Important:** if you will omit `--ifd -i bios` for flashing, you will brick +your machine, because your backup has `FF`s in place of `fd` and `me` regions. +Flash only `bios` region! ## Removing protections (practice) -The original boot script writes 0xE009 to HSFS. FLOCKDN is 15th bit, so let's write 0x6009 instead: +The original boot script writes 0xE009 to HSFS. FLOCKDN is 15th bit, so let's +write 0x6009 instead: Run this: ``` @@ -336,41 +391,68 @@ Bingo! Now you can flash coreboot (or anything else) with flashrom. -Remember to flash only `bios` region (use `--ifd -i bios -N`). `fd` and `me` are still not writable. +Remember to flash only `bios` region (use `--ifd -i bios -N`). `fd` and `me` are +still not writable. -**Note:** if you're flashing coreboot for the first time, you should have an external SPI programmer just in case. It will help you recover if you flash non-working ROM. +**Note:** if you're flashing coreboot for the first time, you should have an +external SPI programmer just in case. It will help you recover if you flash +non-working ROM. ## About Intel ME -Unlocking PRx doesn't allow you to flash ME or Flash Descriptor, so you cannot use [me_cleaner](https://github.com/corna/me_cleaner). Both `me` and `fd` regions will still be write-protected even if you flash coreboot. For now, the best way to get rid of ME is to flash me_cleaned firmware externally. +Unlocking PRx doesn't allow you to flash ME or Flash Descriptor, so you cannot +use [me_cleaner](https://github.com/corna/me_cleaner). Both `me` and `fd` +regions will still be write-protected even if you flash coreboot. For now, the +best way to get rid of ME is to flash me_cleaned firmware externally. -As an alternative, you can use Software Temporary Disable Mode. This is ME's built-in mechanism that BIOS may use to "ask" ME to disable itself after next reboot. In this mode ME stops at BUP phase. This mode is preserved between reboots. Working patch for coreboot is [available](https://review.coreboot.org/c/coreboot/+/37115). +As an alternative, you can use Software Temporary Disable Mode. This is ME's +built-in mechanism that BIOS may use to "ask" ME to disable itself after next +reboot. In this mode ME stops at BUP phase. This mode is preserved between +reboots. Working patch for coreboot is +[available](https://review.coreboot.org/c/coreboot/+/37115). Some possible future solutions are described below. #### HMRFPO (won't work) -**HMRFPO** (Host ME Region Flash Protection Override) is a command BIOS can use to unlock ME region on SPI flash for writing. Vendor can disable it during manufacturing. Unfortunately it's disabled on ThinkPads and can't be used. +**HMRFPO** (Host ME Region Flash Protection Override) is a command BIOS can use +to unlock ME region on SPI flash for writing. Vendor can disable it during +manufacturing. Unfortunately it's disabled on ThinkPads and can't be used. #### HDA_SDO (not implemented) -It is possible to make flash descriptor writable for one boot by asserting HDA_SDO pin high on boot. It should be possible to flash unlocked descriptor while in this state, and that should open ability to flash ME afterwards. [See here for more info](#hda_sdogpio33). +It is possible to make flash descriptor writable for one boot by asserting +HDA_SDO pin high on boot. It should be possible to flash unlocked descriptor +while in this state, and that should open ability to flash ME afterwards. +[See here for more info](#hda_sdogpio33). # Sandy Bridge series (X220, T420, etc.): WIP -S3 Boot Scripts are unprotected on these models too (even on the most recent BIOS versions), but it's not useful, because FLOCKDN and SPI protected ranges are set by **LenovoFlashProtectPei** UEFI module. It is trivial to patch it, but it resides in protected range, so it can only be flashed externally. +S3 Boot Scripts are unprotected on these models too (even on the most recent +BIOS versions), but it's not useful, because FLOCKDN and SPI protected ranges +are set by **LenovoFlashProtectPei** UEFI module. It is trivial to patch it, but +it resides in protected range, so it can only be flashed externally. -Currently there are no known methods to unlock PRs on these devices internally, but investigation is ongoing. +Currently there are no known methods to unlock PRs on these devices internally, +but investigation is ongoing. # Penryn and Nehalem series (X200, T400, X201, T410, etc.): WIP -Currently, the only known way to flash these models without external SPI programmer is by using GPIO33. It is not properly documented yet, and no scripts to automate the process were written. There was a success story though: a user from #coreboot/#libreboot IRC channels has successfully corebooted his X201 without touching the SPI chip. +Currently, the only known way to flash these models without external SPI +programmer is by using GPIO33. It is not properly documented yet, and no scripts +to automate the process were written. There was a success story though: a user +from #coreboot/#libreboot IRC channels has successfully corebooted his X201 +without touching the SPI chip. Progress is tracked [here](https://notabug.org/libreboot/libreboot/issues/689). # Common methods ## HDA_SDO/GPIO33 -There's known Intel "feature", sometimes called "pinmod": you can make flash descriptor writable for one boot by asserting HDA_SDO pin on the motherboard high (on older platforms, you need to assert GPIO33 pin low) at boot time. **Writable flash descriptor** sometimes **allows to flash whole BIOS region** using a couple of neat tricks. I will show this using X220 as an example. +There's known Intel "feature", sometimes called "pinmod": you can make flash +descriptor writable for one boot by asserting HDA_SDO pin on the motherboard +high (on older platforms, you need to assert GPIO33 pin low) at boot time. +**Writable flash descriptor** sometimes **allows to flash whole BIOS region** +using a couple of neat tricks. I will show this using X220 as an example. This is SPI flash layout on X220: ``` @@ -379,30 +461,45 @@ This is SPI flash layout on X220: 00003000:004fffff me 00001000:00002fff gbe ``` -Lenovo BIOS protects, using PR0 register, only small (but critical) part of it: `0x00780000-0x1ffffff`. +Lenovo BIOS protects, using PR0 register, only small (but critical) part of it: +`0x00780000-0x1ffffff`. -> PR0 defines the end of protected range as `0x1ffffff`, but since it's 8MB chip and `bios` ends at `0x007fffff`, `0x00780000-0x007fffff` is what actually is protected. This is the last 512K. +> PR0 defines the end of protected range as `0x1ffffff`, but since it's 8MB chip +and `bios` ends at `0x007fffff`, `0x00780000-0x007fffff` is what actually is +protected. This is the last 512K. As you can see, `0x00500000-0x0077ffff` part is totally writable. Since flash descriptor is writable too, here is what we can do: - patch flash descriptor: - redefine `bios` as `00500000:0077ffff` using ifdtool; - - define the rest of it (`00780000:007fffff`) as `pd` (Platform Data). This is **required**, otherwise you will not be able to flash it in future; + - define the rest of it (`00780000:007fffff`) as `pd` (Platform Data). This is + **required**, otherwise you will not be able to flash it in future; - unlock FD and ME regions (`ifdtool -u`); -- build and flash (small enough) coreboot ROM to this region (must be careful and make sure that reset vector is at the end of our custom region and not at the end of 8MB ROM; use dd or ifdtool for that); +- build and flash (small enough) coreboot ROM to this region (must be careful + and make sure that reset vector is at the end of our custom region and not at + the end of 8MB ROM; use dd or ifdtool for that); - flash modified descriptor; - power off (new FD takes effect after cold boot); - wait a few seconds and power on. -After this, new FD will be in effect and coreboot will be loaded from `0x00500000-0x0077ffff` region, instead of Lenovo BIOS. At this point whole `0x00500000-0x007fffff` will be writable and you will be able to flash coreboot again or patched vendor BIOS (don't forget to revert `fd` changes regarding the `bios` region). +After this, new FD will be in effect and coreboot will be loaded from +`0x00500000-0x0077ffff` region, instead of Lenovo BIOS. At this point whole +`0x00500000-0x007fffff` will be writable and you will be able to flash coreboot +again or patched vendor BIOS (don't forget to revert `fd` changes regarding the +`bios` region). -A user from #coreboot/#libreboot IRC channels was able to flash his X201 internally using the idea described above. However, this is not for mass use yet: we need to write scripts to automate the process, locate HDA_SDO or GPIO33 pins on all motherboards in interest, take their photos and explain, what to do with what. +A user from #coreboot/#libreboot IRC channels was able to flash his X201 +internally using the idea described above. However, this is not for mass use +yet: we need to write scripts to automate the process, locate HDA_SDO or GPIO33 +pins on all motherboards in interest, take their photos and explain, what to do +with what. # Credits -**Rafal Wojtczuk** and **Corey Kallenberg** for discovering the S3 Boot Scripts vulnerability +**Rafal Wojtczuk** and **Corey Kallenberg** for discovering the S3 Boot Scripts +vulnerability -[pgera](https://github.com/hamishcoleman/thinkpad-ec/issues/70#issuecomment-417903315) for the initial research and working solution +[pgera](https://github.com/hamishcoleman/thinkpad-ec/issues/70#issuecomment-417903315) +for the initial research and working solution Lenovo for fake rollback protection - |