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# Config file for the ThinCan dbe61
target dbe61
mainboard artecgroup/dbe61
# HACK to get the right TSC support.
option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
## ROM_SIZE is the total number of bytes allocated for coreboot use
## (normal AND fallback images and payloads).
## leave 36k for vsa and 32K for video ROM
#option ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024
#No VGA for now
option ROM_SIZE = 1024*512 - 36*1024
# ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
## not including any payload.
option ROM_IMAGE_SIZE=64*1024
option FALLBACK_SIZE = ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 9
option MAXIMUM_CONSOLE_LOGLEVEL = 9
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option COREBOOT_EXTRA_VERSION=".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"
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