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## This file is part of the coreboot project.
##
## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config MAINBOARD_HAS_CHROMEOS
def_bool n
menu "ChromeOS"
depends on MAINBOARD_HAS_CHROMEOS
config CHROMEOS
bool "Build for ChromeOS"
default n
select TPM
select BOOTMODE_STRAPS
help
Enable ChromeOS specific features like the GPIO sub table in
the coreboot table. NOTE: Enabling this option on an unsupported
board will most likely break your build.
if CHROMEOS
config VBNV_OFFSET
hex
default 0x26
depends on PC80_SYSTEM
help
CMOS offset for VbNv data. This value must match cmos.layout
in the mainboard directory, minus 14 bytes for the RTC.
config VBNV_SIZE
hex
default 0x10
depends on PC80_SYSTEM
help
CMOS storage size for VbNv data. This value must match cmos.layout
in the mainboard directory.
config CHROMEOS_RAMOOPS
bool "Reserve space for Chrome OS ramoops"
default y
config CHROMEOS_RAMOOPS_DYNAMIC
bool "Allocate RAM oops buffer in cbmem"
default n
depends on CHROMEOS_RAMOOPS
config CHROMEOS_RAMOOPS_RAM_START
hex "Physical address of preserved RAM"
default 0x00f00000
depends on CHROMEOS_RAMOOPS && !CHROMEOS_RAMOOPS_DYNAMIC
config CHROMEOS_RAMOOPS_RAM_SIZE
hex "Size of preserved RAM"
default 0x00100000
depends on CHROMEOS_RAMOOPS
config FLASHMAP_OFFSET
hex "Flash Map Offset"
default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
default 0
help
Offset of flash map in firmware image
config VBOOT_VERIFY_FIRMWARE
bool "Verify firmware with vboot."
default n
select RELOCATABLE_MODULES
help
Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the ramstage
and boot loader.
config VBOOT2_VERIFY_FIRMWARE
bool "Firmware Verification with vboot2"
default n
depends on CHROMEOS
help
Enabling VBOOT2_VERIFY_FIRMWARE will use vboot2 to verify the romstage
and boot loader.
config EC_SOFTWARE_SYNC
bool "Enable EC software sync"
default n
depends on VBOOT_VERIFY_FIRMWARE
help
EC software sync is a mechanism where the AP helps the EC verify its
firmware similar to how vboot verifies the main system firmware. This
option selects whether depthcharge should support EC software sync.
config VIRTUAL_DEV_SWITCH
bool "Virtual developer switch support"
default n
depends on VBOOT_VERIFY_FIRMWARE
help
Whether this platform has a virtual developer switch.
config VBOOT_BOOT_LOADER_INDEX
hex "Bootloader component index"
default 0
depends on VBOOT_VERIFY_FIRMWARE
help
This is the index of the bootloader component in the verified
firmware block.
config VBOOT_RAMSTAGE_INDEX
hex "Ramstage component index"
default 1
depends on VBOOT_VERIFY_FIRMWARE
help
This is the index of the ramstage component in the verified
firmware block.
config VBOOT_REFCODE_INDEX
hex "Reference code firmware index"
default 1
depends on VBOOT_VERIFY_FIRMWARE
help
This is the index of the reference code component in the verified
firmware block.
config NO_TPM_RESUME
bool
default n
help
On some boards the TPM stays powered up in S3. On those
boards, booting Windows will break if the TPM resume command
is sent during an S3 resume.
endif
endmenu
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