1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
|
/**
* @file
*
* SB Initialization.
*
* Init IOAPIC/IOMMU/Misc NB features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
#include "AmdSbLib.h"
#ifndef B1_IMAGE
/*----------------------------------------------------------------------------------------*/
/**
* sbBeforePciInit - Config Southbridge before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbBeforePciInit (
IN AMDSBCFG* pConfig
)
{
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n"));
RecordSbConfigPtr ( (UINT32) ((UINTN) (pConfig)));
CheckEfuse (pConfig);
ValidateFchVariant (pConfig);
imcEnableSurebootTimer (pConfig);
commonInitEarlyPost (pConfig);
commonInitEarlyBoot (pConfig);
#ifndef NO_EC_SUPPORT
ecInitBeforePciEnum (pConfig);
#endif
usbInitBeforePciEnum (pConfig); // USB POST TIME Only
sataInitBeforePciEnum (pConfig); // Init SATA class code and PHY
gecInitBeforePciEnum (pConfig); // Init GEC
azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio
sbPcieGppEarlyInit (pConfig); // Gpp port init
abSpecialSetBeforePciEnum (pConfig);
hwmInit (pConfig);
TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n"));
}
/**
* sbAfterPciInit - Config Southbridge after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbAfterPciInit (
IN AMDSBCFG* pConfig
)
{
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n"));
imcEnableSurebootTimer (pConfig);
usbInitAfterPciInit (pConfig); // Init USB MMIO
sataInitAfterPciEnum (pConfig); // SATA port enumeration
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
hwmUpdateData (pConfig);
TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n"));
}
/**
* sbMidPostInit - Config Southbridge during middle of POST
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbMidPostInit (
IN AMDSBCFG* pConfig
)
{
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbMidPostInit \n"));
imcEnableSurebootTimer (pConfig);
sataInitMidPost (pConfig);
TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbMidPostInit \n"));
}
/*----------------------------------------------------------------------------------------*/
/**
* sbLatePost - Prepare Southbridge to boot to OS.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbLatePost (
IN AMDSBCFG* pConfig
)
{
// UINT16 dwVar;
BUILDPARAM *pStaticOptions;
pStaticOptions = &(pConfig->BuildParameters);
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
commonInitLateBoot (pConfig);
sataInitLatePost (pConfig);
gecInitLatePost (pConfig);
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
#ifndef NO_EC_SUPPORT
ecInitLatePost (pConfig);
#endif
sbPcieGppLateInit (pConfig);
hwmImcInit (pConfig);
// hwmSbtsiAutoPollingOff (pConfig);
imcDisarmSurebootTimer (pConfig);
usbInitLate (pConfig); // Init USB
StressResetModeLate (pConfig); //
}
/*----------------------------------------------------------------------------------------*/
/**
* sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbBeforePciRestoreInit (
IN AMDSBCFG* pConfig
)
{
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n"));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
pConfig->S3Resume = 1;
ValidateFchVariant (pConfig);
commonInitEarlyBoot (pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB
abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers
usbInitBeforePciEnum (pConfig); // USB POST TIME Only
sataInitBeforePciEnum (pConfig);
gecInitBeforePciEnum (pConfig); // Init GEC
azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio
sbPcieGppEarlyInit (pConfig); // Gpp port init
abSpecialSetBeforePciEnum (pConfig);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
}
/*----------------------------------------------------------------------------------------*/
/**
* sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbAfterPciRestoreInit (
IN AMDSBCFG* pConfig
)
{
BUILDPARAM *pStaticOptions;
pConfig->S3Resume = 1;
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
pStaticOptions = &(pConfig->BuildParameters);
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
commonInitLateBoot (pConfig);
sataInitAfterPciEnum (pConfig);
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
sataInitLatePost (pConfig);
c3PopupSetting (pConfig);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
hwmInit (pConfig);
hwmImcInit (pConfig);
}
/*----------------------------------------------------------------------------------------*/
/**
* sbSmmAcpiOn - Config Southbridge during ACPI_ON
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbSmmAcpiOn (
IN AMDSBCFG* pConfig
)
{
// Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest
// recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows
AMDSBCFG* pTmp; //lx-dummy for /W4 build
pTmp = pConfig;
// Disable Power Button SMI
RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGAC, AccWidthUint8, ~(BIT6), 0);
// USB workaroud
// x00[0] = 1;
// x04[31] = 0, x04[0] = 1;
// x08[31] = 0, x08[7] = 0;
// x0C[31] = 0, x0C[7] = 0,
// x10[31] = 0, x10[0] = 1;
// x14[31] = 0, x14[0] = 1;
// x18[31] = 0, x18[7] = 0;
// x1C[31] = 0,
// x20[31] = 0,
//RWMEM (0x00, AccWidthUint32, 0, BIT0);
//RWMEM (0x04, AccWidthUint32, 0, BIT0);
//RWMEM (0x08, AccWidthUint32, 0, 0);
//RWMEM (0x0C, AccWidthUint32, 0, 0);
//RWMEM (0x10, AccWidthUint32, 0, BIT0);
//RWMEM (0x14, AccWidthUint32, 0, BIT0);
//RWMEM (0x18, AccWidthUint32, 0, 0);
//RWMEM (0x1C, AccWidthUint32, 0, 0);
//RWMEM (0x20, AccWidthUint32, 0, 0);
}
#endif
/*----------------------------------------------------------------------------------------*/
/**
* Call Back routine.
*
*
*
* @param[in] Func Callback ID.
* @param[in] Data Callback specific data.
* @param[in] pConfig Southbridge configuration structure pointer.
*/
UINTN
CallBackToOEM (
IN UINT32 Func,
IN UINT32 Data,
IN AMDSBCFG* pConfig
)
{
UINT32 Result;
Result = 0;
if ( pConfig->StdHeader.CALLBACK.CalloutPtr == NULL ) return Result;
TRACE ((DMSG_SB_TRACE, "Calling %lx ( % x, % x, % x)\n", pConfig->StdHeader.CalloutPtr, Func, Data, pConfig));
Result = (*(SBCIM_HOOK_ENTRY*) (UINTN)&pConfig->StdHeader.CALLBACK.CalloutPtr) ( Func, Data, pConfig);
TRACE ((DMSG_SB_TRACE, "SB Hook Status [ % x]\n", Result));
return Result;
}
|
