1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
|
/* $NoKeywords:$ */
/**
* @file
*
* Register definitions
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 87271 $ @e \$Date: 2013-01-31 10:11:23 -0600 (Thu, 31 Jan 2013) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _GNBREGISTERS_CV2_H_
#define _GNBREGISTERS_CV2_H_
#define SMC_MSG_FIRMWARE_AUTH 0
#ifndef WRAP_SPACE
#define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x))
#endif
#ifndef CORE_SPACE
#define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x))
#endif
#ifndef PHY_SPACE
#define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x))
#endif
#ifndef PIF_SPACE
#define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x))
#endif
// **** D0F0xFC_x01 Register Definition ****
// Address
#define D0F0xFC_x01_ADDRESS 0x01
// **** D0F0xFC_x02 Register Definition ****
// Address
#define D0F0xFC_x02_ADDRESS 0x02
// **** D0F0xFC_x10 Register Definition ****
// Address
#define D0F0xFC_x10_ADDRESS 0x10
// Type
#define D0F0xFC_x10_TYPE TYPE_D0F0xFC
// Field Data
#define D0F0xFC_x10_BrExtIntrGrp_OFFSET 0
#define D0F0xFC_x10_BrExtIntrGrp_WIDTH 3
#define D0F0xFC_x10_BrExtIntrGrp_MASK 0x7
#define D0F0xFC_x10_Reserved_3_3_OFFSET 3
#define D0F0xFC_x10_Reserved_3_3_WIDTH 1
#define D0F0xFC_x10_Reserved_3_3_MASK 0x8
#define D0F0xFC_x10_BrExtIntrSwz_OFFSET 4
#define D0F0xFC_x10_BrExtIntrSwz_WIDTH 2
#define D0F0xFC_x10_BrExtIntrSwz_MASK 0x30
#define D0F0xFC_x10_Reserved_15_6_OFFSET 6
#define D0F0xFC_x10_Reserved_15_6_WIDTH 10
#define D0F0xFC_x10_Reserved_15_6_MASK 0xFFC0
#define D0F0xFC_x10_BrIntIntrMap_OFFSET 16
#define D0F0xFC_x10_BrIntIntrMap_WIDTH 5
#define D0F0xFC_x10_BrIntIntrMap_MASK 0x1F0000
#define D0F0xFC_x10_Reserved_31_21_OFFSET 21
#define D0F0xFC_x10_Reserved_31_21_WIDTH 11
#define D0F0xFC_x10_Reserved_31_21_MASK 0xFFE00000
/// D0F0xFC_x10
typedef union {
struct { ///<
UINT32 BrExtIntrGrp:3; ///<
UINT32 Reserved_3_3:1; ///<
UINT32 BrExtIntrSwz:2; ///<
UINT32 Reserved_15_6:10; ///<
UINT32 BrIntIntrMap:5; ///<
UINT32 Reserved_31_21:11; ///<
} Field;
UINT32 Value;
} D0F0xFC_x10_STRUCT;
// **** D0F0xB8 Register Definition ****
// Address
#define D0F0xB8_ADDRESS 0xb8
// **** DxF0xE4_xC1 Register Definition ****
// Address
#define D2FxxE4_xC1_ADDRESS 0xc1
// Type
#define D2FxxE4_xC1_TYPE TYPE_D4F0xE4
// Field Data
#define D2FxxE4_xC1_StrapReverseLanes_OFFSET 0
#define D2FxxE4_xC1_StrapReverseLanes_WIDTH 1
#define D2FxxE4_xC1_StrapReverseLanes_MASK 0x1
#define D2FxxE4_xC1_StrapE2EPrefixEn_OFFSET 1
#define D2FxxE4_xC1_StrapE2EPrefixEn_WIDTH 1
#define D2FxxE4_xC1_StrapE2EPrefixEn_MASK 0x2
#define D2FxxE4_xC1_StrapExtendedFmtSupported_OFFSET 2
#define D2FxxE4_xC1_StrapExtendedFmtSupported_WIDTH 1
#define D2FxxE4_xC1_StrapExtendedFmtSupported_MASK 0x4
#define D2FxxE4_xC1_Reserved_31_3_OFFSET 3
#define D2FxxE4_xC1_Reserved_31_3_WIDTH 29
#define D2FxxE4_xC1_Reserved_31_3_MASK 0xfffffff8
// Type
// Address
#define D0F0xE4_WRAP_0046_ADDRESS 0x46
// Address
#define D0F0xE4_WRAP_8040_ADDRESS 0x8040
// **** D0F0xE4_WRAP_8062 Register Definition ****
// Address
#define D0F0xE4_WRAP_8062_ADDRESS 0x8062
/// D0F0xE4_WRAP_8062
typedef union {
struct { ///<
UINT32 ReconfigureEn:1 ; ///<
UINT32 Reserved_1_1:1 ; ///<
UINT32 ResetPeriod:3 ; ///<
UINT32 Reserved_9_5:5 ; ///<
UINT32 BlockOnIdle:1 ; ///<
UINT32 ConfigXferMode:1 ; ///<
UINT32 Reserved_31_12:20; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_WRAP_8062_STRUCT;
// Type
#define D0F0xE4_WRAP_8040_TYPE TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8040_OwnSlice_OFFSET 0
#define D0F0xE4_WRAP_8040_OwnSlice_WIDTH 1
#define D0F0xE4_WRAP_8040_OwnSlice_MASK 0x1
// **** D0F0xBC_x1F630 Register Definition ****
// Address
#define D0F0xBC_x1F630_ADDRESS 0x1f630
// Type
#define D0F0xBC_x1F630_TYPE TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET 8
#define D0F0xBC_x1F630_RECONF_WRAPPER_WIDTH 8
#define D0F0xBC_x1F630_RECONF_WRAPPER_MASK 0x00ff00
// **** D0F0xE4_WRAP_8011 Register Definition ****
// Address
#define D0F0xE4_WRAP_8011_ADDRESS 0x8011
// Type
#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0
#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6
#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3F
#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6
#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1
#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40
#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7
#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80
#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8
#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1
#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100
#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9
#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200
#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10
#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6
#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xFC00
#define D0F0xE4_WRAP_8011_Bitfield_16_16_OFFSET 16
#define D0F0xE4_WRAP_8011_Bitfield_16_16_WIDTH 1
#define D0F0xE4_WRAP_8011_Bitfield_16_16_MASK 0x10000
#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17
#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6
#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7E0000
#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23
#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1
#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000
#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24
#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000
#define D0F0xE4_WRAP_8011_Reserved_25_25_OFFSET 25
#define D0F0xE4_WRAP_8011_Reserved_25_25_WIDTH 1
#define D0F0xE4_WRAP_8011_Reserved_25_25_MASK 0x2000000
#define D0F0xE4_WRAP_8011_Reserved_31_26_OFFSET 26
#define D0F0xE4_WRAP_8011_Reserved_31_26_WIDTH 6
#define D0F0xE4_WRAP_8011_Reserved_31_26_MASK 0xFC000000
/// D0F0xE4_WRAP_8011
typedef union {
struct { ///<
UINT32 TxclkDynGateLatency:6; ///<
UINT32 TxclkPermGateEven:1; ///<
UINT32 TxclkDynGateEnable:1; ///<
UINT32 TxclkPermStop:1; ///<
UINT32 TxclkRegsGateEnable:1; ///<
UINT32 TxclkRegsGateLatency:6; ///<
UINT32 Bitfield_16_16:1; ///<
UINT32 TxclkPermGateLatency:6; ///<
UINT32 Reserved_23_23:1; ///<
UINT32 TxclkLcntGateEnable:1; ///<
UINT32 Reserved_25_25:1; ///<
UINT32 Reserved_31_26:6; ///<
} Field;
UINT32 Value;
} D0F0xE4_WRAP_8011_STRUCT;
// **** D0F0xE4_WRAP_8016 Register Definition ****
// Address
#define D0F0xE4_WRAP_8016_ADDRESS 0x8016
// Type
#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4
/// D0F0xE4_WRAP_8016
typedef union {
struct { ///<
UINT32 CalibAckLatency:6 ; ///<
UINT32 Reserved_15_6:10; ///<
UINT32 LclkDynGateLatency:6 ; ///<
UINT32 LclkGateFree:1 ; ///<
UINT32 LclkDynGateEnable:1 ; ///<
UINT32 Reserved_31_24:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_WRAP_8016_STRUCT;
// **** D0F0xE4_CORE_0011 Register Definition ****
// Address
#define D0F0xE4_CORE_0011_ADDRESS 0x11
#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET 0
#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH 4
#define D0F0xE4_CORE_0011_DynClkLatency_MASK 0xf
// **** D0F0xE4_PIF_0010 Register Definition ****
// Address
#define D0F0xE4_PIF_0010_ADDRESS 0x10
// Type
#define D0F0xE4_PIF_0010_TYPE TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET 0
#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH 4
#define D0F0xE4_PIF_0010_Reserved_3_0_MASK 0xf
#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET 4
#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH 1
#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK 0x10
#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET 5
#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH 1
#define D0F0xE4_PIF_0010_Reserved_5_5_MASK 0x20
#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET 6
#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH 1
#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK 0x40
#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET 7
#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH 1
#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK 0x80
#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET 8
#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH 9
#define D0F0xE4_PIF_0010_Reserved_16_8_MASK 0x1ff00
#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET 17
#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH 3
#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK 0xe0000
#define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET 23
#define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH 9
#define D0F0xE4_PIF_0010_Reserved_31_23_MASK 0xff800000
/// D0F0xE4_PIF_0010
typedef union {
struct { ///<
UINT32 Reserved_3_0:4 ; ///<
UINT32 EiDetCycleMode:1 ; ///<
UINT32 Reserved_5_5:1 ; ///<
UINT32 RxDetectFifoResetMode:1 ; ///<
UINT32 RxDetectTxPwrMode:1 ; ///<
UINT32 Reserved_16_8:9 ; ///<
UINT32 Ls2ExitTime:3 ; ///<
UINT32 :3 ; ///<
UINT32 Reserved_31_23:9 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_PIF_0010_STRUCT;
// **** D2FxxE4_xA4 Register Definition ****
// Address
#define D2FxxE4_xA4_ADDRESS 0xa4
// Type
#define D2FxxE4_xA4_TYPE TYPE_D4F0xE4
// Field Data
#define D2FxxE4_xA4_LcGen2EnStrap_OFFSET 0
#define D2FxxE4_xA4_LcGen2EnStrap_WIDTH 1
#define D2FxxE4_xA4_LcGen2EnStrap_MASK 0x1
#define D2FxxE4_xA4_Reserved_5_1_OFFSET 1
#define D2FxxE4_xA4_Reserved_5_1_WIDTH 5
#define D2FxxE4_xA4_Reserved_5_1_MASK 0x3e
#define D2FxxE4_xA4_LcForceDisSwSpeedChange_OFFSET 6
#define D2FxxE4_xA4_LcForceDisSwSpeedChange_WIDTH 1
#define D2FxxE4_xA4_LcForceDisSwSpeedChange_MASK 0x40
#define D2FxxE4_xA4_Reserved_8_7_OFFSET 7
#define D2FxxE4_xA4_Reserved_8_7_WIDTH 2
#define D2FxxE4_xA4_Reserved_8_7_MASK 0x180
#define D2FxxE4_xA4_LcInitiateLinkSpeedChange_OFFSET 9
#define D2FxxE4_xA4_LcInitiateLinkSpeedChange_WIDTH 1
#define D2FxxE4_xA4_LcInitiateLinkSpeedChange_MASK 0x200
#define D2FxxE4_xA4_Reserved_11_10_OFFSET 10
#define D2FxxE4_xA4_Reserved_11_10_WIDTH 2
#define D2FxxE4_xA4_Reserved_11_10_MASK 0xc00
#define D2FxxE4_xA4_LcSpeedChangeAttemptFailed_OFFSET 12
#define D2FxxE4_xA4_LcSpeedChangeAttemptFailed_WIDTH 1
#define D2FxxE4_xA4_LcSpeedChangeAttemptFailed_MASK 0x1000
#define D2FxxE4_xA4_Reserved_18_13_OFFSET 13
#define D2FxxE4_xA4_Reserved_18_13_WIDTH 6
#define D2FxxE4_xA4_Reserved_18_13_MASK 0x7e000
#define D2FxxE4_xA4_LcOtherSideSupportsGen2_OFFSET 19
#define D2FxxE4_xA4_LcOtherSideSupportsGen2_WIDTH 1
#define D2FxxE4_xA4_LcOtherSideSupportsGen2_MASK 0x80000
#define D2FxxE4_xA4_Reserved_26_20_OFFSET 20
#define D2FxxE4_xA4_Reserved_26_20_WIDTH 7
#define D2FxxE4_xA4_Reserved_26_20_MASK 0x7f00000
#define D2FxxE4_xA4_LcMultUpstreamAutoSpdChngEn_OFFSET 27
#define D2FxxE4_xA4_LcMultUpstreamAutoSpdChngEn_WIDTH 1
#define D2FxxE4_xA4_LcMultUpstreamAutoSpdChngEn_MASK 0x8000000
#define D2FxxE4_xA4_Reserved_31_28_OFFSET 28
#define D2FxxE4_xA4_Reserved_31_28_WIDTH 4
#define D2FxxE4_xA4_Reserved_31_28_MASK 0xf0000000
/// D2FxxE4_xA4
typedef union {
struct { ///<
UINT32 LcGen2EnStrap:1 ; ///<
UINT32 Reserved_5_1:5 ; ///<
UINT32 LcForceDisSwSpeedChange:1 ; ///<
UINT32 Reserved_8_7:2 ; ///<
UINT32 LcInitiateLinkSpeedChange:1 ; ///<
UINT32 Reserved_11_10:2 ; ///<
UINT32 LcSpeedChangeAttemptFailed:1 ; ///<
UINT32 Reserved_18_13:6 ; ///<
UINT32 LcOtherSideSupportsGen2:1 ; ///<
UINT32 Reserved_26_20:7 ; ///<
UINT32 LcMultUpstreamAutoSpdChngEn:1 ; ///<
UINT32 Reserved_31_28:4 ; ///<
} Field; ///<
UINT32 Value; ///<
} D2FxxE4_xA4_STRUCT;
// **** D2FxxE4_xC0 Register Definition ****
// Address
#define D2FxxE4_xC0_ADDRESS 0xc0
// Type
#define D2FxxE4_xC0_TYPE TYPE_D4F0xE4
// Field Data
#define D2FxxE4_xC0_Reserved_12_0_OFFSET 0
#define D2FxxE4_xC0_Reserved_12_0_WIDTH 13
#define D2FxxE4_xC0_Reserved_12_0_MASK 0x1fff
#define D2FxxE4_xC0_StrapForceCompliance_OFFSET 13
#define D2FxxE4_xC0_StrapForceCompliance_WIDTH 1
#define D2FxxE4_xC0_StrapForceCompliance_MASK 0x2000
#define D2FxxE4_xC0_Reserved_14_14_OFFSET 14
#define D2FxxE4_xC0_Reserved_14_14_WIDTH 1
#define D2FxxE4_xC0_Reserved_14_14_MASK 0x4000
#define D2FxxE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET 15
#define D2FxxE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH 1
#define D2FxxE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK 0x8000
#define D2FxxE4_xC0_Reserved_31_16_OFFSET 16
#define D2FxxE4_xC0_Reserved_31_16_WIDTH 16
#define D2FxxE4_xC0_Reserved_31_16_MASK 0xffff0000
/// D2FxxE4_xC0
typedef union {
struct { ///<
UINT32 Reserved_12_0:13; ///<
UINT32 StrapForceCompliance:1 ; ///<
UINT32 Reserved_14_14:1 ; ///<
UINT32 StrapAutoRcSpeedNegotiationDis:1 ; ///<
UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
} D2FxxE4_xC0_STRUCT;
// **** D2Fxx88 Register Definition ****
// Address
#define D2Fxx88_ADDRESS 0x88
// Type
#define D2Fxx88_TYPE TYPE_D4F0
// Field Data
#define D2Fxx88_TargetLinkSpeed_OFFSET 0
#define D2Fxx88_TargetLinkSpeed_WIDTH 4
#define D2Fxx88_TargetLinkSpeed_MASK 0xf
#define D2Fxx88_EnterCompliance_OFFSET 4
#define D2Fxx88_EnterCompliance_WIDTH 1
#define D2Fxx88_EnterCompliance_MASK 0x10
#define D2Fxx88_HwAutonomousSpeedDisable_OFFSET 5
#define D2Fxx88_HwAutonomousSpeedDisable_WIDTH 1
#define D2Fxx88_HwAutonomousSpeedDisable_MASK 0x20
#define D2Fxx88_SelectableDeemphasis_OFFSET 6
#define D2Fxx88_SelectableDeemphasis_WIDTH 1
#define D2Fxx88_SelectableDeemphasis_MASK 0x40
#define D2Fxx88_XmitMargin_OFFSET 7
#define D2Fxx88_XmitMargin_WIDTH 3
#define D2Fxx88_XmitMargin_MASK 0x380
#define D2Fxx88_EnterModCompliance_OFFSET 10
#define D2Fxx88_EnterModCompliance_WIDTH 1
#define D2Fxx88_EnterModCompliance_MASK 0x400
#define D2Fxx88_ComplianceSOS_OFFSET 11
#define D2Fxx88_ComplianceSOS_WIDTH 1
#define D2Fxx88_ComplianceSOS_MASK 0x800
#define D2Fxx88_ComplianceDeemphasis_OFFSET 12
#define D2Fxx88_ComplianceDeemphasis_WIDTH 1
#define D2Fxx88_ComplianceDeemphasis_MASK 0x1000
#define D2Fxx88_Reserved_15_13_OFFSET 13
#define D2Fxx88_Reserved_15_13_WIDTH 3
#define D2Fxx88_Reserved_15_13_MASK 0xe000
#define D2Fxx88_CurDeemphasisLevel_OFFSET 16
#define D2Fxx88_CurDeemphasisLevel_WIDTH 1
#define D2Fxx88_CurDeemphasisLevel_MASK 0x10000
#define D2Fxx88_Reserved_31_17_OFFSET 17
#define D2Fxx88_Reserved_31_17_WIDTH 15
#define D2Fxx88_Reserved_31_17_MASK 0xfffe0000
/// D2Fxx88
typedef union {
struct { ///<
UINT32 TargetLinkSpeed:4 ; ///<
UINT32 EnterCompliance:1 ; ///<
UINT32 HwAutonomousSpeedDisable:1 ; ///<
UINT32 SelectableDeemphasis:1 ; ///<
UINT32 XmitMargin:3 ; ///<
UINT32 EnterModCompliance:1 ; ///<
UINT32 ComplianceSOS:1 ; ///<
UINT32 ComplianceDeemphasis:1 ; ///<
UINT32 Reserved_15_13:3 ; ///<
UINT32 CurDeemphasisLevel:1 ; ///<
UINT32 Reserved_31_17:15; ///<
} Field; ///<
UINT32 Value; ///<
} D2Fxx88_STRUCT;
// **** D0F0xE4_WRAP_0803 Register Definition ****
// Address
#define D0F0xE4_WRAP_0803_ADDRESS 0x803
// Type
#define D0F0xE4_WRAP_0803_TYPE TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET 0
#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH 5
#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK 0x1f
#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET 5
#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH 1
#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK 0x20
#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET 6
#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH 26
#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK 0xffffffc0
/// D0F0xE4_WRAP_0803
typedef union {
struct { ///<
UINT32 Reserved_4_0:5 ; ///<
UINT32 StrapBifDeemphasisSel:1 ; ///<
UINT32 Reserved_31_6:26; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_WRAP_0803_STRUCT;
/*
* Needed by GnbNbInitLibV4.c
*/
// **** D0F0x60 Register Definition ****
// Address
#define D0F0x60_ADDRESS 0x60
// **** D0F0x90 Register Definition ****
// Address
#define D0F0x90_ADDRESS 0x90
// **** D0F0x64_x19 Register Definition ****
// Address
#define D0F0x64_x19_ADDRESS 0x19
// **** D0F0x64_x1A Register Definition ****
// Address
#define D0F0x64_x1A_ADDRESS 0x1a
/// D0F0xBC_x80010000
typedef union {
UINT32 Value; ///<
} GRC1_STRUCT;
// **** D0F0xE4_CORE_0010 Register Definition ****
// Address
#define D0F0xE4_CORE_0010_ADDRESS 0x10
// Type
#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4
// Field Data
#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0
#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1
#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1
#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET 1
#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH 8
#define D0F0xE4_CORE_0010_Reserved_8_1_MASK 0x1fe
#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9
#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1
#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200
#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET 10
#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH 3
#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK 0x1c00
#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET 13
#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH 19
#define D0F0xE4_CORE_0010_Reserved_31_13_MASK 0xffffe000
/// D0F0xE4_CORE_0010
typedef union {
struct { ///<
UINT32 HwInitWrLock:1 ; ///<
UINT32 Reserved_8_1:8 ; ///<
UINT32 UmiNpMemWrite:1 ; ///<
UINT32 RxSbAdjPayloadSize:3 ; ///<
UINT32 Reserved_31_13:19; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_CORE_0010_STRUCT;
// **** D0F0x94 Register Definition ****
// Address
#define D0F0x94_ADDRESS 0x94
// **** D0F0x98_x3A Register Definition ****
// Address
#define D0F0x98_x3A_ADDRESS 0x3a
// **** D18F0x110 Register Definition ****
// Address
#define D18F0x110_ADDRESS 0x110
// **** D0F0x98_x06 Register Definition ****
// Address
#define D0F0x98_x06_ADDRESS 0x6
#define D0F0x98_x06_UmiNpMemWrEn_OFFSET 26
#define D0F0x98_x06_UmiNpMemWrEn_WIDTH 1
#define D0F0x98_x06_UmiNpMemWrEn_MASK 0x4000000
/*
* Needed by GnbNbInitLibV4.c - end
*/
/*
* Needed by GnbIommuScratch.c
*/
/*
* Needed by GnbIommuScratch.c - end
*/
/*
* Needed by GnbIoapic.c
*/
// **** D0F0xF8 Register Definition ****
// Address
#define D0F0xF8_ADDRESS 0xf8
// **** D0F0xFC_x00 Register Definition ****
// Address
#define D0F0xFC_x00_ADDRESS 0x0
// Type
#define D0F0xFC_x00_TYPE TYPE_D0F0xFC
// Field Data
#define D0F0xFC_x00_IoapicEnable_OFFSET 0
#define D0F0xFC_x00_IoapicEnable_WIDTH 1
#define D0F0xFC_x00_IoapicEnable_MASK 0x01
#define D0F0xFC_x00_Reserved_1_1_OFFSET 2
#define D0F0xFC_x00_Reserved_1_1_WIDTH 1
#define D0F0xFC_x00_Reserved_1_1_MASK 0x02
#define D0F0xFC_x00_IoapicIdExtEn_OFFSET 3
#define D0F0xFC_x00_IoapicIdExtEn_WIDTH 1
#define D0F0xFC_x00_IoapicIdExtEn_MASK 0x04
#define D0F0xFC_x00_Reserved_3_3_OFFSET 4
#define D0F0xFC_x00_Reserved_3_3_WIDTH 1
#define D0F0xFC_x00_Reserved_3_3_MASK 0x08
#define D0F0xFC_x00_IoapicSbFeatureEn_OFFSET 4
#define D0F0xFC_x00_IoapicSbFeatureEn_WIDTH 1
#define D0F0xFC_x00_IoapicSbFeatureEn_MASK 0x10
#define D0F0xFC_x00_Reserved_31_5_OFFSET 5
#define D0F0xFC_x00_Reserved_31_5_WIDTH 27
#define D0F0xFC_x00_Reserved_31_5_MASK 0xffffffe0
/// D0F0xFC_x00
typedef union {
struct { ///<
UINT32 IoapicEnable:1 ; ///<
UINT32 Reserved_1_1:1 ; ///<
UINT32 IoapicIdExtEn:1 ; ///<
UINT32 Reserved_3_3:1 ; ///<
UINT32 IoapicSbFeatureEn:1 ; ///<
UINT32 Reserved_31_5:27; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xFC_x00_STRUCT;
/*
* Needed by GnbIoapic.c - end
*/
/*
* Needed by GnbPcieInitLibV5
*/
// **** D0F0xE4_WRAP_8021 Register Definition ****
// Address
#define D0F0xE4_WRAP_8021_ADDRESS 0x8021
// **** D0F0xCC_x01 Register Definition ****
// Address
#define D0F0xCC_x01_ADDRESS 0x1
// Type
#define D0F0xCC_x01_TYPE TYPE_D0F0xCC
// Field Data
#define D0F0xCC_x01_BridgeDis_OFFSET 0
#define D0F0xCC_x01_BridgeDis_WIDTH 1
#define D0F0xCC_x01_BridgeDis_MASK 0x1
#define D0F0xCC_x01_Reserved_1_1_OFFSET 1
#define D0F0xCC_x01_Reserved_1_1_WIDTH 1
#define D0F0xCC_x01_Reserved_1_1_MASK 0x2
#define D0F0xCC_x01_CfgDis_OFFSET 2
#define D0F0xCC_x01_CfgDis_WIDTH 1
#define D0F0xCC_x01_CfgDis_MASK 0x4
#define D0F0xCC_x01_P2pDis_OFFSET 3
#define D0F0xCC_x01_P2pDis_WIDTH 1
#define D0F0xCC_x01_P2pDis_MASK 0x8
#define D0F0xCC_x01_Reserved_15_4_OFFSET 4
#define D0F0xCC_x01_Reserved_15_4_WIDTH 12
#define D0F0xCC_x01_Reserved_15_4_MASK 0xfff0
#define D0F0xCC_x01_ExtDevPlug_OFFSET 16
#define D0F0xCC_x01_ExtDevPlug_WIDTH 1
#define D0F0xCC_x01_ExtDevPlug_MASK 0x10000
#define D0F0xCC_x01_ExtDevCsrEn_OFFSET 17
#define D0F0xCC_x01_ExtDevCsrEn_WIDTH 1
#define D0F0xCC_x01_ExtDevCsrEn_MASK 0x20000
#define D0F0xCC_x01_CsrEnable_OFFSET 18
#define D0F0xCC_x01_CsrEnable_WIDTH 1
#define D0F0xCC_x01_CsrEnable_MASK 0x40000
#define D0F0xCC_x01_SetPowEn_OFFSET 20
#define D0F0xCC_x01_SetPowEn_WIDTH 1
#define D0F0xCC_x01_SetPowEn_MASK 0x100000
#define D0F0xCC_x01_Reserved_22_21_OFFSET 21
#define D0F0xCC_x01_Reserved_22_21_WIDTH 2
#define D0F0xCC_x01_Reserved_22_21_MASK 0x600000
#define D0F0xCC_x01_ApicEnable_OFFSET 23
#define D0F0xCC_x01_ApicEnable_WIDTH 1
#define D0F0xCC_x01_ApicEnable_MASK 0x800000
#define D0F0xCC_x01_ApicRange_OFFSET 24
#define D0F0xCC_x01_ApicRange_WIDTH 8
#define D0F0xCC_x01_ApicRange_MASK 0xff000000
/// D0F0xCC_x1
typedef union {
struct { ///<
UINT32 BridgeDis:1 ; ///<
UINT32 Reserved_1_1:2 ; ///<
UINT32 CfgDis:1 ; ///<
UINT32 P2pDis:1 ; ///<
UINT32 Reserved_15_4:12; ///<
UINT32 ExtDevPlug:1 ; ///<
UINT32 ExtDevCsrEn:1 ; ///<
UINT32 CsrEnable:1 ; ///<
UINT32 Reserved_19_19:1 ; ///<
UINT32 SetPowEn:1 ; ///<
UINT32 Reserved_22_21:2 ; ///<
UINT32 ApicEnable:1 ; ///<
UINT32 ApicRange:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xCC_x01_STRUCT;
// **** D0F0xC8 Register Definition ****
// Address
#define D0F0xC8_ADDRESS 0xc8
// Type
#define D0F0xC8_TYPE TYPE_D0F0
// Field Data
#define D0F0xC8_NB_DEV_IND_ADDR_OFFSET 0
#define D0F0xC8_NB_DEV_IND_ADDR_WIDTH 7
#define D0F0xC8_NB_DEV_IND_ADDR_MASK 0x7F
#define D0F0xC8_Reserved_15_7_OFFSET 7
#define D0F0xC8_Reserved_15_7_WIDTH 9
#define D0F0xC8_Reserved_15_7_MASK 0xFF80
#define D0F0xC8_NB_DEV_IND_SEL_OFFSET 16
#define D0F0xC8_NB_DEV_IND_SEL_WIDTH 8
#define D0F0xC8_NB_DEV_IND_SEL_MASK 0xFF0000
#define D0F0xC8_Reserved_31_24_OFFSET 24
#define D0F0xC8_Reserved_31_24_WIDTH 8
#define D0F0xC8_Reserved_31_24_MASK 0xFF000000
/// D0F0xC8
typedef union {
struct { ///<
UINT32 NB_DEV_IND_ADDR:7; ///<
UINT32 Reserved_15_7:9; ///<
UINT32 NB_DEV_IND_SEL:8; ///<
UINT32 Reserved_31_24:8; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xC8_STRUCT;
#ifdef _GNBPCIEINITLIBV4_H_
// **** D0F0xE4_WRAP_8014 Register Definition ****
// Address
#define D0F0xE4_WRAP_8014_ADDRESS 0x8014
/// D0F0xE4_WRAP_8014
typedef union {
struct { ///<
UINT32 TxclkPermGateEnable:1 ; ///<
UINT32 TxclkPrbsGateEnable:1 ; ///<
UINT32 DdiGatePifA1xEnable:1 ; ///<
UINT32 DdiGatePifB1xEnable:1 ; ///<
UINT32 DdiGatePifC1xEnable:1 ; ///<
UINT32 DdiGatePifD1xEnable:1 ; ///<
UINT32 Reserved_7_6:2 ; ///<
UINT32 DdiGatePifA2p5xEnable:1 ; ///<
UINT32 DdiGatePifB2p5xEnable:1 ; ///<
UINT32 DdiGatePifC2p5xEnable:1 ; ///<
UINT32 DdiGatePifD2p5xEnable:1 ; ///<
UINT32 PcieGatePifA1xEnable:1 ; ///<
UINT32 PcieGatePifB1xEnable:1 ; ///<
UINT32 PcieGatePifC1xEnable:1 ; ///<
UINT32 PcieGatePifD1xEnable:1 ; ///<
UINT32 PcieGatePifA2p5xEnable:1 ; ///<
UINT32 PcieGatePifB2p5xEnable:1 ; ///<
UINT32 PcieGatePifC2p5xEnable:1 ; ///<
UINT32 PcieGatePifD2p5xEnable:1 ; ///<
UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///<
UINT32 Reserved_23_21:3 ; ///<
UINT32 DdiGateDigAEnable:1 ; ///<
UINT32 DdiGateDigBEnable:1 ; ///<
UINT32 DdiGateDigCEnable:1 ; ///<
UINT32 DdiGateDigDEnable:1 ; ///<
UINT32 SpareRegRw:4 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_WRAP_8014_STRUCT;
#endif
#ifdef _GNBPCIEINITLIBV5_H_ // KV version of WRAP_8014
// **** D0F0xE4_WRAP_8014 Register Definition ****
// Address
#define D0F0xE4_WRAP_8014_ADDRESS 0x8014
// Type
#define D0F0xE4_WRAP_8014_TYPE TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0
#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1
#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1
#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2
#define D0F0xE4_WRAP_8014_DdiPifa1xGateEnable_OFFSET 2
#define D0F0xE4_WRAP_8014_DdiPifa1xGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_DdiPifa1xGateEnable_MASK 0x4
#define D0F0xE4_WRAP_8014_DdiPifb1xGateEnable_OFFSET 3
#define D0F0xE4_WRAP_8014_DdiPifb1xGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_DdiPifb1xGateEnable_MASK 0x8
#define D0F0xE4_WRAP_8014_DdiPifc1xGateEnable_OFFSET 4
#define D0F0xE4_WRAP_8014_DdiPifc1xGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_DdiPifc1xGateEnable_MASK 0x10
#define D0F0xE4_WRAP_8014_DdiPifd1xGateEnable_OFFSET 5
#define D0F0xE4_WRAP_8014_DdiPifd1xGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_DdiPifd1xGateEnable_MASK 0x20
#define D0F0xE4_WRAP_8014_Reserved_11_6_OFFSET 6
#define D0F0xE4_WRAP_8014_Reserved_11_6_WIDTH 6
#define D0F0xE4_WRAP_8014_Reserved_11_6_MASK 0xfc0
#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12
#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000
#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_OFFSET 13
#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_MASK 0x2000
#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_OFFSET 14
#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_MASK 0x4000
#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_OFFSET 15
#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_MASK 0x8000
#define D0F0xE4_WRAP_8014_Reserved_19_16_OFFSET 16
#define D0F0xE4_WRAP_8014_Reserved_19_16_WIDTH 4
#define D0F0xE4_WRAP_8014_Reserved_19_16_MASK 0xf0000
#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20
#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1
#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000
#define D0F0xE4_WRAP_8014_Reserved_23_21_OFFSET 21
#define D0F0xE4_WRAP_8014_Reserved_23_21_WIDTH 3
#define D0F0xE4_WRAP_8014_Reserved_23_21_MASK 0xe00000
#define D0F0xE4_WRAP_8014_DdiDigaGateEnable_OFFSET 24
#define D0F0xE4_WRAP_8014_DdiDigaGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_DdiDigaGateEnable_MASK 0x1000000
#define D0F0xE4_WRAP_8014_DdiDigbGateEnable_OFFSET 25
#define D0F0xE4_WRAP_8014_DdiDigbGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_DdiDigbGateEnable_MASK 0x2000000
#define D0F0xE4_WRAP_8014_DdiDigcGateEnable_OFFSET 26
#define D0F0xE4_WRAP_8014_DdiDigcGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_DdiDigcGateEnable_MASK 0x4000000
#define D0F0xE4_WRAP_8014_DdiDigdGateEnable_OFFSET 27
#define D0F0xE4_WRAP_8014_DdiDigdGateEnable_WIDTH 1
#define D0F0xE4_WRAP_8014_DdiDigdGateEnable_MASK 0x8000000
#define D0F0xE4_WRAP_8014_SpareRegRw_OFFSET 28
#define D0F0xE4_WRAP_8014_SpareRegRw_WIDTH 4
#define D0F0xE4_WRAP_8014_SpareRegRw_MASK 0xf0000000
/// D0F0xE4_WRAP_8014
typedef union {
struct { ///<
UINT32 TxclkPermGateEnable:1 ; ///<
UINT32 TxclkPrbsGateEnable:1 ; ///<
UINT32 DdiPifa1xGateEnable:1 ; ///<
UINT32 DdiPifb1xGateEnable:1 ; ///<
UINT32 DdiPifc1xGateEnable:1 ; ///<
UINT32 DdiPifd1xGateEnable:1 ; ///<
UINT32 Reserved_11_6:6 ; ///<
UINT32 PcieGatePifA1xEnable:1 ; ///<
UINT32 PcieGatePifB1xEnable:1 ; ///<
UINT32 PcieGatePifC1xEnable:1 ; ///<
UINT32 PcieGatePifD1xEnable:1 ; ///<
UINT32 Reserved_19_16:4 ; ///<
UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///<
UINT32 Reserved_23_21:3 ; ///<
UINT32 DdiDigaGateEnable:1 ; ///<
UINT32 DdiDigbGateEnable:1 ; ///<
UINT32 DdiDigcGateEnable:1 ; ///<
UINT32 DdiDigdGateEnable:1 ; ///<
UINT32 SpareRegRw:4 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_WRAP_8014_STRUCT;
// **** D0F0xE4_WRAP_8029 Register Definition ****
// Address
#define D0F0xE4_WRAP_8029_ADDRESS 0x8029
// Type
#define D0F0xE4_WRAP_8029_TYPE TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8029_LaneEnable_OFFSET 0
#define D0F0xE4_WRAP_8029_LaneEnable_WIDTH 16
#define D0F0xE4_WRAP_8029_LaneEnable_MASK 0xFFFF
#define D0F0xE4_WRAP_8029_Reserved_31_16_OFFSET 16
#define D0F0xE4_WRAP_8029_Reserved_31_16_WIDTH 16
#define D0F0xE4_WRAP_8029_Reserved_31_16_MASK 0xFFFF0000
/// D0F0xE4_WRAP_8029
typedef union {
struct { ///<
UINT32 LaneEnable:16; ///<
UINT32 Reserved_31_16:16; ///<
} Field;
UINT32 Value;
} D0F0xE4_WRAP_8029_STRUCT;
#endif
#ifdef _GNBPCIETRAININGV2_H_
// **** DxFxx68 Register Definition ****
// Address
#define DxFxx68_ADDRESS 0x68
// Type
#define DxFxx68_TYPE TYPE_D2F1
// Field Data
#define DxFxx68_PmControl_OFFSET 0
#define DxFxx68_PmControl_WIDTH 2
#define DxFxx68_PmControl_MASK 0x3
#define DxFxx68_Reserved_2_2_OFFSET 2
#define DxFxx68_Reserved_2_2_WIDTH 1
#define DxFxx68_Reserved_2_2_MASK 0x4
#define DxFxx68_ReadCplBoundary_OFFSET 3
#define DxFxx68_ReadCplBoundary_WIDTH 1
#define DxFxx68_ReadCplBoundary_MASK 0x8
#define DxFxx68_LinkDis_OFFSET 4
#define DxFxx68_LinkDis_WIDTH 1
#define DxFxx68_LinkDis_MASK 0x10
#define DxFxx68_RetrainLink_OFFSET 5
#define DxFxx68_RetrainLink_WIDTH 1
#define DxFxx68_RetrainLink_MASK 0x20
#define DxFxx68_CommonClockCfg_OFFSET 6
#define DxFxx68_CommonClockCfg_WIDTH 1
#define DxFxx68_CommonClockCfg_MASK 0x40
#define DxFxx68_ExtendedSync_OFFSET 7
#define DxFxx68_ExtendedSync_WIDTH 1
#define DxFxx68_ExtendedSync_MASK 0x80
#define DxFxx68_ClockPowerManagementEn_OFFSET 8
#define DxFxx68_ClockPowerManagementEn_WIDTH 1
#define DxFxx68_ClockPowerManagementEn_MASK 0x100
#define DxFxx68_HWAutonomousWidthDisable_OFFSET 9
#define DxFxx68_HWAutonomousWidthDisable_WIDTH 1
#define DxFxx68_HWAutonomousWidthDisable_MASK 0x200
#define DxFxx68_LinkBWManagementEn_OFFSET 10
#define DxFxx68_LinkBWManagementEn_WIDTH 1
#define DxFxx68_LinkBWManagementEn_MASK 0x400
#define DxFxx68_LinkAutonomousBWIntEn_OFFSET 11
#define DxFxx68_LinkAutonomousBWIntEn_WIDTH 1
#define DxFxx68_LinkAutonomousBWIntEn_MASK 0x800
#define DxFxx68_Reserved_15_12_OFFSET 12
#define DxFxx68_Reserved_15_12_WIDTH 4
#define DxFxx68_Reserved_15_12_MASK 0xF000
#define DxFxx68_LinkSpeed_OFFSET 16
#define DxFxx68_LinkSpeed_WIDTH 4
#define DxFxx68_LinkSpeed_MASK 0xF0000
#define DxFxx68_NegotiatedLinkWidth_OFFSET 20
#define DxFxx68_NegotiatedLinkWidth_WIDTH 6
#define DxFxx68_NegotiatedLinkWidth_MASK 0x3F00000
#define DxFxx68_Reserved_26_26_OFFSET 26
#define DxFxx68_Reserved_26_26_WIDTH 1
#define DxFxx68_Reserved_26_26_MASK 0x4000000
#define DxFxx68_LinkTraining_OFFSET 27
#define DxFxx68_LinkTraining_WIDTH 1
#define DxFxx68_LinkTraining_MASK 0x8000000
#define DxFxx68_SlotClockCfg_OFFSET 28
#define DxFxx68_SlotClockCfg_WIDTH 1
#define DxFxx68_SlotClockCfg_MASK 0x10000000
#define DxFxx68_DlActive_OFFSET 29
#define DxFxx68_DlActive_WIDTH 1
#define DxFxx68_DlActive_MASK 0x20000000
#define DxFxx68_LinkBWManagementStatus_OFFSET 30
#define DxFxx68_LinkBWManagementStatus_WIDTH 1
#define DxFxx68_LinkBWManagementStatus_MASK 0x40000000
#define DxFxx68_LinkAutonomousBWStatus_OFFSET 31
#define DxFxx68_LinkAutonomousBWStatus_WIDTH 1
#define DxFxx68_LinkAutonomousBWStatus_MASK 0x80000000
/// DxFxx68
typedef union {
struct { ///<
UINT32 PmControl:2; ///<
UINT32 Reserved_2_2:1; ///<
UINT32 ReadCplBoundary:1; ///<
UINT32 LinkDis:1; ///<
UINT32 RetrainLink:1; ///<
UINT32 CommonClockCfg:1; ///<
UINT32 ExtendedSync:1; ///<
UINT32 ClockPowerManagementEn:1; ///<
UINT32 HWAutonomousWidthDisable:1; ///<
UINT32 LinkBWManagementEn:1; ///<
UINT32 LinkAutonomousBWIntEn:1; ///<
UINT32 Reserved_15_12:4; ///<
UINT32 LinkSpeed:4; ///<
UINT32 NegotiatedLinkWidth:6; ///<
UINT32 Reserved_26_26:1; ///<
UINT32 LinkTraining:1; ///<
UINT32 SlotClockCfg:1; ///<
UINT32 DlActive:1; ///<
UINT32 LinkBWManagementStatus:1; ///<
UINT32 LinkAutonomousBWStatus:1; ///<
} Field;
UINT32 Value;
} DxFxx68_STRUCT;
// **** D0F0xE4_WRAP_0800 Register Definition ****
// Address
#define D0F0xE4_WRAP_0800_ADDRESS 0x800
// Type
#define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0
#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1
#define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1
#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1
#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31
#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xFFFFFFFE
/// D0F0xE4_WRAP_0800
typedef union {
struct { ///<
UINT32 HoldTraining:1; ///<
UINT32 Reserved_31_1:31; ///<
} Field;
UINT32 Value;
} D0F0xE4_WRAP_0800_STRUCT;
// **** DxFxx128 Register Definition ****
// Address
#define DxFxx128_ADDRESS 0x128
// Type
#define DxFxx128_TYPE TYPE_D2F1
// Field Data
#define DxFxx128_Reserved_15_0_OFFSET 0
#define DxFxx128_Reserved_15_0_WIDTH 16
#define DxFxx128_Reserved_15_0_MASK 0xFFFF
#define DxFxx128_PortArbTableStatus_OFFSET 16
#define DxFxx128_PortArbTableStatus_WIDTH 1
#define DxFxx128_PortArbTableStatus_MASK 0x10000
#define DxFxx128_VcNegotiationPending_OFFSET 17
#define DxFxx128_VcNegotiationPending_WIDTH 1
#define DxFxx128_VcNegotiationPending_MASK 0x20000
#define DxFxx128_Reserved_31_18_OFFSET 18
#define DxFxx128_Reserved_31_18_WIDTH 14
#define DxFxx128_Reserved_31_18_MASK 0xFFFC0000
/// DxFxx128
typedef union {
struct { ///<
UINT32 Reserved_15_0:16; ///<
UINT32 PortArbTableStatus:1; ///<
UINT32 VcNegotiationPending:1; ///<
UINT32 Reserved_31_18:14; ///<
} Field;
UINT32 Value;
} DxFxx128_STRUCT;
// **** DxFxx18 Register Definition ****
// Address
#define DxFxx18_ADDRESS 0x18
// Type
#define DxFxx18_TYPE TYPE_D2F1
// **** DxFxx20 Register Definition ****
// Address
#define DxFxx20_ADDRESS 0x20
// Type
#define DxFxx20_TYPE TYPE_D2F1
// **** DxFxx24 Register Definition ****
// Address
#define DxFxx24_ADDRESS 0x24
// Type
#define DxFxx24_TYPE TYPE_D2F1
// **** D0F0x04 Register Definition ****
// Address
#define D0F0x04_ADDRESS 0x4
// Type
#define D0F0x04_TYPE TYPE_D0F0
// Field Data
#define D0F0x04_IoAccessEn_OFFSET 0
#define D0F0x04_IoAccessEn_WIDTH 1
#define D0F0x04_IoAccessEn_MASK 0x1
#define D0F0x04_MemAccessEn_OFFSET 1
#define D0F0x04_MemAccessEn_WIDTH 1
#define D0F0x04_MemAccessEn_MASK 0x2
#define D0F0x04_BusMasterEn_OFFSET 2
#define D0F0x04_BusMasterEn_WIDTH 1
#define D0F0x04_BusMasterEn_MASK 0x4
#define D0F0x04_Reserved_19_3_OFFSET 3
#define D0F0x04_Reserved_19_3_WIDTH 17
#define D0F0x04_Reserved_19_3_MASK 0xFFFF8
#define D0F0x04_CapList_OFFSET 20
#define D0F0x04_CapList_WIDTH 1
#define D0F0x04_CapList_MASK 0x100000
#define D0F0x04_Reserved_31_21_OFFSET 21
#define D0F0x04_Reserved_31_21_WIDTH 11
#define D0F0x04_Reserved_31_21_MASK 0xFFE00000
/// D0F0x04
typedef union {
struct { ///<
UINT32 IoAccessEn:1; ///<
UINT32 MemAccessEn:1; ///<
UINT32 BusMasterEn:1; ///<
UINT32 Reserved_19_3:17; ///<
UINT32 CapList:1; ///<
UINT32 Reserved_31_21:11; ///<
} Field;
UINT32 Value;
} D0F0x04_STRUCT;
#endif
// **** D0F0xE4_PIF_0011 Register Definition ****
// Address
#define D0F0xE4_PIF_0011_ADDRESS 0x11
// Type
#define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0
#define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1
#define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1
#define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1
#define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1
#define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2
#define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2
#define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1
#define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4
#define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3
#define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1
#define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8
#define D0F0xE4_PIF_0011_X2Lane98_OFFSET 4
#define D0F0xE4_PIF_0011_X2Lane98_WIDTH 1
#define D0F0xE4_PIF_0011_X2Lane98_MASK 0x10
#define D0F0xE4_PIF_0011_X2Lane1110_OFFSET 5
#define D0F0xE4_PIF_0011_X2Lane1110_WIDTH 1
#define D0F0xE4_PIF_0011_X2Lane1110_MASK 0x20
#define D0F0xE4_PIF_0011_X2Lane1312_OFFSET 6
#define D0F0xE4_PIF_0011_X2Lane1312_WIDTH 1
#define D0F0xE4_PIF_0011_X2Lane1312_MASK 0x40
#define D0F0xE4_PIF_0011_X2Lane1514_OFFSET 7
#define D0F0xE4_PIF_0011_X2Lane1514_WIDTH 1
#define D0F0xE4_PIF_0011_X2Lane1514_MASK 0x80
#define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8
#define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1
#define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100
#define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9
#define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1
#define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200
#define D0F0xE4_PIF_0011_X4Lane118_OFFSET 10
#define D0F0xE4_PIF_0011_X4Lane118_WIDTH 1
#define D0F0xE4_PIF_0011_X4Lane118_MASK 0x400
#define D0F0xE4_PIF_0011_X4Lane1512_OFFSET 11
#define D0F0xE4_PIF_0011_X4Lane1512_WIDTH 1
#define D0F0xE4_PIF_0011_X4Lane1512_MASK 0x800
#define D0F0xE4_PIF_0011_Reserved_15_12_OFFSET 12
#define D0F0xE4_PIF_0011_Reserved_15_12_WIDTH 4
#define D0F0xE4_PIF_0011_Reserved_15_12_MASK 0xf000
#define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16
#define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1
#define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000
#define D0F0xE4_PIF_0011_X8Lane158_OFFSET 17
#define D0F0xE4_PIF_0011_X8Lane158_WIDTH 1
#define D0F0xE4_PIF_0011_X8Lane158_MASK 0x20000
#define D0F0xE4_PIF_0011_Reserved_19_18_OFFSET 18
#define D0F0xE4_PIF_0011_Reserved_19_18_WIDTH 2
#define D0F0xE4_PIF_0011_Reserved_19_18_MASK 0xc0000
#define D0F0xE4_PIF_0011_X16Lane150_OFFSET 20
#define D0F0xE4_PIF_0011_X16Lane150_WIDTH 1
#define D0F0xE4_PIF_0011_X16Lane150_MASK 0x100000
#define D0F0xE4_PIF_0011_Reserved_24_21_OFFSET 21
#define D0F0xE4_PIF_0011_Reserved_24_21_WIDTH 4
#define D0F0xE4_PIF_0011_Reserved_24_21_MASK 0x1e00000
#define D0F0xE4_PIF_0011_MultiPif_OFFSET 25
#define D0F0xE4_PIF_0011_MultiPif_WIDTH 1
#define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000
#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26
#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6
#define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xfc000000
/// D0F0xE4_PIF_0011
typedef union {
struct { ///<
UINT32 X2Lane10:1 ; ///<
UINT32 X2Lane32:1 ; ///<
UINT32 X2Lane54:1 ; ///<
UINT32 X2Lane76:1 ; ///<
UINT32 X2Lane98:1 ; ///<
UINT32 X2Lane1110:1 ; ///<
UINT32 X2Lane1312:1 ; ///<
UINT32 X2Lane1514:1 ; ///<
UINT32 X4Lane30:1 ; ///<
UINT32 X4Lane74:1 ; ///<
UINT32 X4Lane118:1 ; ///<
UINT32 X4Lane1512:1 ; ///<
UINT32 Reserved_15_12:4 ; ///<
UINT32 X8Lane70:1 ; ///<
UINT32 X8Lane158:1 ; ///<
UINT32 Reserved_19_18:2 ; ///<
UINT32 X16Lane150:1 ; ///<
UINT32 Reserved_24_21:4 ; ///<
UINT32 MultiPif:1 ; ///<
UINT32 Reserved_31_26:6 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_PIF_0011_STRUCT;
// **** D0F0xE4_PIF_0012 Register Definition ****
// Address
#define D0F0xE4_PIF_0012_ADDRESS 0x12
// Type
#define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0
#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3
#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7
#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3
#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1
#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8
#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4
#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3
#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70
#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7
#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3
#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380
#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10
#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3
#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1c00
#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13
#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3
#define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xe000
#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16
#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1
#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000
#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17
#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7
#define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xfe0000
#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24
#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3
#define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000
#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27
#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1
#define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000
#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28
#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1
#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000
#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29
#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3
#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xe0000000
/// D0F0xE4_PIF_0012
typedef union {
struct { ///<
UINT32 TxPowerStateInTxs2:3 ; ///<
UINT32 ForceRxEnInL0s:1 ; ///<
UINT32 RxPowerStateInRxs2:3 ; ///<
UINT32 PllPowerStateInTxs2:3 ; ///<
UINT32 PllPowerStateInOff:3 ; ///<
UINT32 Reserved_15_13:3 ; ///<
UINT32 Tx2p5clkClockGatingEn:1 ; ///<
UINT32 Reserved_23_17:7 ; ///<
UINT32 PllRampUpTime:3 ; ///<
UINT32 Reserved_27_27:1 ; ///<
UINT32 PllPwrOverrideEn:1 ; ///<
UINT32 PllPwrOverrideVal:3 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_PIF_0012_STRUCT;
// **** D0F0xE4_PIF_0017 Register Definition ****
// Address
#define D0F0xE4_PIF_0017_ADDRESS 0x17
// Type
#define D0F0xE4_PIF_0017_TYPE TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PIF_0017_TxPowerStateInTxs2_OFFSET 0
#define D0F0xE4_PIF_0017_TxPowerStateInTxs2_WIDTH 3
#define D0F0xE4_PIF_0017_TxPowerStateInTxs2_MASK 0x7
#define D0F0xE4_PIF_0017_ForceRxEnInL0s_OFFSET 3
#define D0F0xE4_PIF_0017_ForceRxEnInL0s_WIDTH 1
#define D0F0xE4_PIF_0017_ForceRxEnInL0s_MASK 0x8
#define D0F0xE4_PIF_0017_RxPowerStateInRxs2_OFFSET 4
#define D0F0xE4_PIF_0017_RxPowerStateInRxs2_WIDTH 3
#define D0F0xE4_PIF_0017_RxPowerStateInRxs2_MASK 0x70
#define D0F0xE4_PIF_0017_PllPowerStateInTxs2_OFFSET 7
#define D0F0xE4_PIF_0017_PllPowerStateInTxs2_WIDTH 3
#define D0F0xE4_PIF_0017_PllPowerStateInTxs2_MASK 0x380
#define D0F0xE4_PIF_0017_PllPowerStateInOff_OFFSET 10
#define D0F0xE4_PIF_0017_PllPowerStateInOff_WIDTH 3
#define D0F0xE4_PIF_0017_PllPowerStateInOff_MASK 0x1c00
#define D0F0xE4_PIF_0017_Reserved_15_13_OFFSET 13
#define D0F0xE4_PIF_0017_Reserved_15_13_WIDTH 3
#define D0F0xE4_PIF_0017_Reserved_15_13_MASK 0xe000
#define D0F0xE4_PIF_0017_Tx2p5clkClockGatingEn_OFFSET 16
#define D0F0xE4_PIF_0017_Tx2p5clkClockGatingEn_WIDTH 1
#define D0F0xE4_PIF_0017_Tx2p5clkClockGatingEn_MASK 0x10000
#define D0F0xE4_PIF_0017_Reserved_23_17_OFFSET 17
#define D0F0xE4_PIF_0017_Reserved_23_17_WIDTH 7
#define D0F0xE4_PIF_0017_Reserved_23_17_MASK 0xfe0000
#define D0F0xE4_PIF_0017_PllRampUpTime_OFFSET 24
#define D0F0xE4_PIF_0017_PllRampUpTime_WIDTH 3
#define D0F0xE4_PIF_0017_PllRampUpTime_MASK 0x7000000
#define D0F0xE4_PIF_0017_Reserved_27_27_OFFSET 27
#define D0F0xE4_PIF_0017_Reserved_27_27_WIDTH 1
#define D0F0xE4_PIF_0017_Reserved_27_27_MASK 0x8000000
#define D0F0xE4_PIF_0017_PllPwrOverrideEn_OFFSET 28
#define D0F0xE4_PIF_0017_PllPwrOverrideEn_WIDTH 1
#define D0F0xE4_PIF_0017_PllPwrOverrideEn_MASK 0x10000000
#define D0F0xE4_PIF_0017_PllPwrOverrideVal_OFFSET 29
#define D0F0xE4_PIF_0017_PllPwrOverrideVal_WIDTH 3
#define D0F0xE4_PIF_0017_PllPwrOverrideVal_MASK 0xe0000000
/// D0F0xE4_PIF_0017
typedef union {
struct { ///<
UINT32 TxPowerStateInTxs2:3 ; ///<
UINT32 ForceRxEnInL0s:1 ; ///<
UINT32 RxPowerStateInRxs2:3 ; ///<
UINT32 PllPowerStateInTxs2:3 ; ///<
UINT32 PllPowerStateInOff:3 ; ///<
UINT32 Reserved_15_13:3 ; ///<
UINT32 Tx2p5clkClockGatingEn:1 ; ///<
UINT32 Reserved_23_17:7 ; ///<
UINT32 PllRampUpTime:3 ; ///<
UINT32 Reserved_27_27:1 ; ///<
UINT32 PllPwrOverrideEn:1 ; ///<
UINT32 PllPwrOverrideVal:3 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_PIF_0017_STRUCT;
// **** D0F0xE4_CORE_00B0 Register Definition ****
// Address
#define D0F0xE4_CORE_00B0_ADDRESS 0xb0
// Type
#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4
// Field Data
#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0
#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2
#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3
#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2
#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1
#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4
#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET 3
#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH 2
#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK 0x18
#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET 5
#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH 1
#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK 0x20
#define D0F0xE4_CORE_00B0_Bitfield_6_6_MASK 0x40
#define D0F0xE4_CORE_00B0_Reserved_31_7_OFFSET 7
#define D0F0xE4_CORE_00B0_Reserved_31_7_WIDTH 25
#define D0F0xE4_CORE_00B0_Reserved_31_7_MASK 0xffffff80
/// D0F0xE4_CORE_00B0
typedef union {
struct { ///<
UINT32 Reserved_1_0:2 ; ///<
UINT32 StrapF0MsiEn:1 ; ///<
UINT32 Reserved_4_3:2 ; ///<
UINT32 StrapF0AerEn:1 ; ///<
UINT32 Bitfield_6_6:1 ; ///<
UINT32 Reserved_31_7:25; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_CORE_00B0_STRUCT;
typedef union {
struct { ///<
UINT32 Bitfield_0_0:1; ///<
UINT32 Bitfield_1_1:1 ; ///<
UINT32 Reserved_15_2:14; ///<
UINT32 Bitfield_16_16:1; ///<
UINT32 Bitfield_17_17:1 ; ///<
UINT32 Reserved_31_18:14; ///<
} Field; ///<
UINT32 Value; ///<
} GRC2_STRUCT;
#endif
|
