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/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU Cache Flush On Halt Function for Family 16h Kabini.
*
* Contains code to initialize Cache Flush On Halt feature for Family 16h Kabini.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*----------------------------------------------------------------------------
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuPostInit.h"
#include "cpuF16PowerMgmt.h"
#include "F16KbPowerMgmt.h"
#include "cpuFeatures.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBCACHEFLUSHONHALT_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
VOID
SetF16KbCacheFlushOnHaltRegister (
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* P U B L I C F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/* -----------------------------------------------------------------------------*/
/**
* Enable Cpu Cache Flush On Halt Function
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*/
VOID
SetF16KbCacheFlushOnHaltRegister (
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
CSTATE_CTRL1_REGISTER CstateCtrl1;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
// Set F4x118
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
// Set C-state Action Field 0
// bits[11] NbClkGate0 = 0x1
// bits[12] SelfRefr0 = 0x1
CstateCtrl1.NbClkGate0 = 1;
CstateCtrl1.SelfRefr0 = 1;
// Set C-state Action Field 1
// bits[27] NbClkGate1 = 0x1
// bits[28] SelfRefr1 = 0x1
CstateCtrl1.NbClkGate1 = 1;
CstateCtrl1.SelfRefr1 = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
//Override the default setting
IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);
}
}
CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F16KbCacheFlushOnHalt =
{
0,
SetF16KbCacheFlushOnHaltRegister
};
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