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/* $NoKeywords:$ */
/**
* @file
*
* mpseeds.c
*
* A sub-engine extracts WL and HW RxEn seeds from PSCFG tables.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Ps)
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
**/
/*****************************************************************************
*
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
*
* AMD is granting you permission to use this software (the Materials)
* pursuant to the terms and conditions of your Software License Agreement
* with AMD. This header does *NOT* give you permission to use the Materials
* or any rights under AMD's intellectual property. Your use of any portion
* of these Materials shall constitute your acceptance of those terms and
* conditions. If you do not agree to the terms and conditions of the Software
* License Agreement, please do not use any portion of these Materials.
*
* CONFIDENTIALITY: The Materials and all other information, identified as
* confidential and provided to you by AMD shall be kept confidential in
* accordance with the terms and conditions of the Software License Agreement.
*
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
*
* AMD does not assume any responsibility for any errors which may appear in
* the Materials or any other related information provided to you by AMD, or
* result from use of the Materials or any related information.
*
* You agree that you will not reverse engineer or decompile the Materials.
*
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
* further information, software, technical information, know-how, or show-how
* available to you. Additionally, AMD retains the right to modify the
* Materials at any time, without notice, and is not obligated to provide such
* modified Materials to you.
*
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
* subject to the restrictions as set forth in FAR 52.227-14 and
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
* Government constitutes acknowledgement of AMD's proprietary rights in them.
*
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
* direct product thereof will be exported directly or indirectly, into any
* country prohibited by the United States Export Administration Act and the
* regulations thereunder, without the required authorization from the U.S.
* government nor will be used for any purpose prohibited by the same.
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "AdvancedApi.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuFamRegisters.h"
#include "cpuRegisters.h"
#include "OptionMemory.h"
#include "PlatformMemoryConfiguration.h"
#include "mu.h"
#include "ma.h"
#include "mp.h"
#include "merrhdl.h"
#include "GeneralServices.h"
#include "Filecode.h"
CODE_GROUP (G2_PEI)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_MEM_PS_MPSEEDS_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/* -----------------------------------------------------------------------------*/
/**
*
* A sub-function extracts WL and HW RxEn seeds from PSCFG tables
* from a input table
*
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
* @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
*
* @return NBPtr->PsPtr->WLSeedVal
* @return NBPtr->PsPtr->HWRxENSeedVal
*
*/
BOOLEAN
MemPGetTrainingSeeds (
IN OUT MEM_NB_BLOCK *NBPtr,
IN MEM_PSC_TABLE_BLOCK *EntryOfTables
)
{
UINT8 i;
UINT8 MaxDimmPerCh;
UINT8 MaxDimmSlotPerCh;
UINT8 NOD;
UINT8 TableSize;
DIMM_TYPE DimmType;
CPU_LOGICAL_ID LogicalCpuid;
UINT8 PackageType;
UINT8 Seedloop;
UINT8 CH;
PSC_TBL_ENTRY **TblEntryPtr;
PSCFG_SEED_ENTRY *TblPtr;
CH_DEF_STRUCT *CurrentChannel;
CurrentChannel = NBPtr->ChannelPtr;
TblEntryPtr = NULL;
TblPtr = NULL;
TableSize = 0;
PackageType = 0;
LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
MaxDimmSlotPerCh = MaxDimmPerCh - GetMaxSolderedDownDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
CH = 1 << (CurrentChannel->ChannelID);
if (CurrentChannel->RegDimmPresent != 0) {
DimmType = RDIMM_TYPE;
} else if (CurrentChannel->SODimmPresent != 0) {
DimmType = SODIMM_TYPE;
} else if (CurrentChannel->LrDimmPresent != 0) {
DimmType = LRDIMM_TYPE;
} else {
DimmType = UDIMM_TYPE;
}
// Check if it is "SODIMM plus soldered-down DRAM" or "Soldered-down DRAM only" configuration,
// DimmType is changed to 'SODWN_SODIMM_TYPE' if soldered-down DRAM exist
if (MaxDimmSlotPerCh != MaxDimmPerCh) {
// SODIMM plus soldered-down DRAM
DimmType = SODWN_SODIMM_TYPE;
} else if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) {
// Soldered-down DRAM only
DimmType = SODWN_SODIMM_TYPE;
MaxDimmSlotPerCh = 0;
}
NOD = (UINT8) (MaxDimmSlotPerCh != 0) ? (1 << (MaxDimmSlotPerCh - 1)) : _DIMM_NONE;
// Get seed value of WL, then HW RxEn
for (Seedloop = 0; Seedloop < 2; Seedloop++) {
TblEntryPtr = (Seedloop == 0) ? EntryOfTables->TblEntryOfWLSeed : EntryOfTables->TblEntryOfHWRxENSeed;
i = 0;
// Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
while (TblEntryPtr[i] != NULL) {
if (((TblEntryPtr[i])->Header.DimmType & DimmType) != 0) {
//
// Determine if this is the expected NB Type
//
LogicalCpuid = (TblEntryPtr[i])->Header.LogicalCpuid;
PackageType = (TblEntryPtr[i])->Header.PackageType;
if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
TblPtr = (PSCFG_SEED_ENTRY *) ((TblEntryPtr[i])->TBLPtr);
TableSize = (TblEntryPtr[i])->TableSize;
break;
}
}
i++;
}
// Check whether no table entry is found.
if (TblEntryPtr[i] == NULL) {
IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s training seeds Config table\n", (Seedloop == 0) ? "WL" : "HW RxEn");
return FALSE;
}
for (i = 0; i < TableSize; i++) {
if ((TblPtr->DimmPerCh & NOD) != 0) {
if ((TblPtr->Channel & CH) != 0) {
if (Seedloop == 0) {
NBPtr->PsPtr->WLSeedVal = (UINT8) TblPtr->SeedVal;
} else {
NBPtr->PsPtr->HWRxENSeedVal = TblPtr->SeedVal;
}
break;
}
}
TblPtr++;
}
if (i == TableSize) {
IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s seed entries\n\n", (Seedloop == 0) ? "WL" : "HW RxEn");
PutEventLog (AGESA_ERROR, MEM_ERROR_TRAINING_SEED_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
ASSERT (FALSE);
}
return FALSE;
}
}
return TRUE;
}
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