1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
|
/* $NoKeywords:$ */
/**
* @file
*
* PCIe utility. Various supporting functions.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "Ids.h"
#include "amdlib.h"
#include "Gnb.h"
#include "GnbPcie.h"
#include "GnbPcieFamServices.h"
#include "GnbCommonLib.h"
#include "GnbPcieConfig.h"
#include "GnbPcieInitLibV1.h"
#include "GnbRegistersLN.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/// Lane type
typedef enum {
LaneTypeCore, ///< Core Lane
LaneTypePhy, ///< Package Phy Lane
LaneTypeNativePhy ///< Native Phy Lane
} LANE_TYPE;
/// Lane Property
typedef enum {
LanePropertyConfig, ///< Configuration
LanePropertyActive, ///< Active
LanePropertyAllocated ///< Allocated
} LANE_PROPERTY;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
typedef struct {
UINT32 Flags;
PCIE_LINK_SPEED_CAP LinkSpeedCapability;
} PCIE_GLOBAL_GEN_CAP_WORKSPACE;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Get link state history from HW state machine
*
*
*
* @param[in] Engine Pointer to engine config descriptor
* @param[out] History Buffer to save history
* @param[in] Length Buffer length
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieUtilGetLinkHwStateHistory (
IN PCIe_ENGINE_CONFIG *Engine,
OUT UINT8 *History,
IN UINT8 Length,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 ReadLength;
UINT32 LocalHistory [6];
UINT16 Index;
ASSERT (Length <= 16);
ASSERT (Length > 0);
if (Length > 6*4) {
Length = 6*4;
}
ReadLength = (Length + 3) / 4;
for (Index = 0; Index < ReadLength; Index++) {
LocalHistory[Index] = PciePortRegisterRead (
Engine,
DxF0xE4_xA5_ADDRESS + Index,
Pcie
);
}
LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie));
}
/*----------------------------------------------------------------------------------------*/
/**
* Search array for specific pattern
*
*
* @param[in] Buf1 Pointer to source buffer which will be subject of search
* @param[in] Buf1Length Length of the source buffer
* @param[in] Buf2 Pointer to pattern buffer
* @param[in] Buf2Length Length of the pattern buffer
* @retval TRUE Pattern found
* @retval TRUE Pattern not found
*/
BOOLEAN
PcieUtilSearchArray (
IN UINT8 *Buf1,
IN UINTN Buf1Length,
IN UINT8 *Buf2,
IN UINTN Buf2Length
)
{
UINT8 *CurrentBuf1Ptr;
CurrentBuf1Ptr = Buf1;
while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) {
UINT8 *SourceBufPtr;
UINT8 *PatternBufPtr;
UINTN PatternBufLength;
SourceBufPtr = CurrentBuf1Ptr;
PatternBufPtr = Buf2;
PatternBufLength = Buf2Length;
while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0));
if (PatternBufLength == 0) {
return TRUE;
}
CurrentBuf1Ptr++;
}
return FALSE;
}
/*----------------------------------------------------------------------------------------*/
/**
* Check if link reversed
*
*
* @param[in] HwLinkState Check for HW auto link reversal
* @param[in] Engine Pointer to engine config descriptor
* @param[in] Pcie Pointer to PCIe config descriptor
* @retval TRUE if link reversed
*/
BOOLEAN
PcieUtilIsLinkReversed (
IN BOOLEAN HwLinkState,
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 LinkReversal;
LinkReversal = (Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? 1 : 0;
if (HwLinkState) {
DxF0xE4_x50_STRUCT DxF0xE4_x50;
DxF0xE4_x50.Value = PciePortRegisterRead (
Engine,
DxF0xE4_x50_ADDRESS,
Pcie
);
LinkReversal ^= DxF0xE4_x50.Field.PortLaneReversal;
}
return ((LinkReversal & BIT0) != 0) ? TRUE : FALSE;
}
/*----------------------------------------------------------------------------------------*/
/**
* Get link width detected during training
*
*
*
* @param[in] Engine Pointer to engine config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
* @retval Link width
*/
UINT8
PcieUtilGetLinkWidth (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 LinkWidth;
DxF0xE4_xA2_STRUCT DxF0xE4_xA2;
DxF0xE4_xA2.Value = PciePortRegisterRead (
Engine,
DxF0xE4_xA2_ADDRESS,
Pcie
);
switch (DxF0xE4_xA2.Field.LcLinkWidthRd) {
case 0x6:
LinkWidth = 16;
break;
case 0x5:
LinkWidth = 12;
break;
case 0x4:
LinkWidth = 8;
break;
case 0x3:
LinkWidth = 4;
break;
case 0x2:
LinkWidth = 2;
break;
case 0x1:
LinkWidth = 1;
break;
default:
LinkWidth = 0;
}
return LinkWidth;
}
/*----------------------------------------------------------------------------------------*/
/**
* Get bitmap of PCIE engine lane of requested type
*
*
* @param[in] LaneType Lane type
* @param[in] LaneProperty Lane Property
* @param[in] Engine Pointer to engine config descriptor
* @retval Lane bitmap
*/
STATIC UINT32
PcieUtilGetPcieEngineLaneBitMap (
IN LANE_TYPE LaneType,
IN LANE_PROPERTY LaneProperty,
IN PCIe_ENGINE_CONFIG *Engine
)
{
UINT32 LaneBitmap;
UINT8 Width;
UINT16 Offset;
UINT16 LoPhylane;
UINT16 HiPhylane;
PCIe_PLATFORM_CONFIG *Pcie;
Width = 0;
Offset = 0;
LaneBitmap = 0;
Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
if (PcieConfigIsPcieEngine (Engine)) {
if (LaneType == LaneTypeCore && LaneProperty == LanePropertyConfig) {
Width = PcieConfigGetNumberOfCoreLane (Engine);
Offset = Engine->Type.Port.StartCoreLane;
LaneBitmap = ((1 << Width) - 1) << Offset;
} else if (PcieConfigIsEngineAllocated (Engine)) {
if (LaneType == LaneTypeNativePhy) {
LaneBitmap = PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine);
LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine);
} else {
if (LaneType == LaneTypeCore) {
if (LaneProperty == LanePropertyActive) {
Width = PcieUtilGetLinkWidth (Engine, Pcie);
Offset = PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane;
} else if (LaneProperty == LanePropertyAllocated) {
Width = PcieConfigGetNumberOfPhyLane (Engine);
Offset = PcieUtilIsLinkReversed (FALSE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane;
}
}
if (LaneType == LaneTypePhy) {
LoPhylane = PcieLibGetLoPhyLane (Engine);
HiPhylane = PcieLibGetHiPhyLane (Engine);
if (LaneProperty == LanePropertyActive) {
Width = PcieUtilGetLinkWidth (Engine, Pcie);
Offset = (PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (HiPhylane - Width + 1) : LoPhylane) - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
} else if (LaneProperty == LanePropertyAllocated) {
Width = PcieConfigGetNumberOfPhyLane (Engine);
Offset = LoPhylane - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
}
}
LaneBitmap = ((1 << Width) - 1) << Offset;
}
}
}
return LaneBitmap;
}
/*----------------------------------------------------------------------------------------*/
/**
* Get bitmap of PCIE engine lane of requested type
*
*
* @param[in] LaneType Lane type
* @param[in] LaneProperty Lane Property
* @param[in] Engine Pointer to engine config descriptor
* @retval Lane bitmap
*/
STATIC UINT32
PcieUtilGetDdiEngineLaneBitMap (
IN LANE_TYPE LaneType,
IN LANE_PROPERTY LaneProperty,
IN PCIe_ENGINE_CONFIG *Engine
)
{
UINT32 LaneBitmap;
UINT8 Width;
UINT16 Offset;
Width = 0;
Offset = 0;
LaneBitmap = 0;
if (PcieConfigIsDdiEngine (Engine)) {
if (PcieConfigIsEngineAllocated (Engine)) {
if (LaneType == LaneTypePhy && ((LaneProperty == LanePropertyActive && (Engine->InitStatus & INIT_STATUS_DDI_ACTIVE)) || (LaneProperty == LanePropertyAllocated))) {
Width = PcieConfigGetNumberOfPhyLane (Engine);
Offset = PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
LaneBitmap = ((1 << Width) - 1) << Offset;
}
if (LaneType == LaneTypeNativePhy) {
LaneBitmap = PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine);
LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine);
}
}
}
return LaneBitmap;
}
/*----------------------------------------------------------------------------------------*/
/**
* Get bitmap of engine lane of requested type
*
*
* @param[in] IncludeLaneType Include Lane type
* @param[in] ExcludeLaneType Exclude Lane type
* @param[in] Engine Pointer to engine config descriptor
* @retval Lane bitmap
*/
UINT32
PcieUtilGetEngineLaneBitMap (
IN UINT32 IncludeLaneType,
IN UINT32 ExcludeLaneType,
IN PCIe_ENGINE_CONFIG *Engine
)
{
UINT32 LaneBitmap;
LaneBitmap = 0;
if (IncludeLaneType & LANE_TYPE_PCIE_LANES) {
if (IncludeLaneType & LANE_TYPE_PCIE_CORE_CONFIG) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine);
}
if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
}
if (IncludeLaneType & (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE)) {
if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
} else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
} else {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyActive, Engine);
}
}
}
if ((IncludeLaneType & LANE_TYPE_PCIE_SB_CORE_CONFIG) && PcieConfigIsSbPcieEngine (Engine)) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine);
}
if ((IncludeLaneType & LANE_TYPE_PCIE_CORE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
}
if (IncludeLaneType & LANE_TYPE_PCIE_PHY) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine);
}
if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
}
if (IncludeLaneType & (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE)) {
if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
} else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
} else {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine);
}
}
}
if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
}
}
if (IncludeLaneType & LANE_TYPE_DDI_LANES) {
if (IncludeLaneType & LANE_TYPE_DDI_PHY) {
LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine);
}
if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE) {
LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
}
if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) {
LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine);
}
}
if (ExcludeLaneType != 0) {
LaneBitmap &= (~PcieUtilGetEngineLaneBitMap (ExcludeLaneType, 0, Engine));
}
return LaneBitmap;
}
/*----------------------------------------------------------------------------------------*/
/**
* Get bitmap of phy lane confugred for master pll
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @retval Lane bitmap
*/
STATIC UINT32
PcieUtilGetMasterPllLaneBitMap (
IN PCIe_WRAPPER_CONFIG *Wrapper
)
{
if (Wrapper->MasterPll != 0) {
return 0xf << (Wrapper->MasterPll - 0xA) * 4;
}
return 0;
}
/*----------------------------------------------------------------------------------------*/
/**
* Get bitmap of Wrapper lane of requested type
*
*
* @param[in] IncludeLaneType Include Lane type
* @param[in] ExcludeLaneType Exclude Lane type
* @param[in] Wrapper Pointer to wrapper config descriptor
* @retval Lane bitmap
*/
UINT32
PcieUtilGetWrapperLaneBitMap (
IN UINT32 IncludeLaneType,
IN UINT32 ExcludeLaneType,
IN PCIe_WRAPPER_CONFIG *Wrapper
)
{
PCIe_ENGINE_CONFIG *EngineList;
UINT32 LaneBitmap;
EngineList = PcieConfigGetChildEngine (Wrapper);
LaneBitmap = 0;
if ((IncludeLaneType | ExcludeLaneType) != 0) {
if ((IncludeLaneType & LANE_TYPE_ALL) == LANE_TYPE_ALL) {
LaneBitmap = (1 << (Wrapper->NumberOfLanes)) - 1;
if (ExcludeLaneType != 0) {
LaneBitmap &= (~PcieUtilGetWrapperLaneBitMap (ExcludeLaneType, 0, Wrapper));
}
} else {
while (EngineList != NULL) {
LaneBitmap |= PcieUtilGetEngineLaneBitMap (IncludeLaneType, ExcludeLaneType, EngineList);
EngineList = PcieLibGetNextDescriptor (EngineList);
}
if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) {
LaneBitmap |= PcieUtilGetMasterPllLaneBitMap (Wrapper);
}
if ((ExcludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) {
LaneBitmap &= (~PcieUtilGetMasterPllLaneBitMap (Wrapper));
}
}
}
return LaneBitmap;
}
/*----------------------------------------------------------------------------------------*/
/**
* Program port register table
*
*
*
* @param[in] Table Pointer to table
* @param[in] Length number of entries
* @param[in] Engine Pointer to engine config descriptor
* @param[in] S3Save Save for S3 flag
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
PciePortProgramRegisterTable (
IN PCIE_PORT_REGISTER_ENTRY *Table,
IN UINTN Length,
IN PCIe_ENGINE_CONFIG *Engine,
IN BOOLEAN S3Save,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINTN Index;
UINT32 Value;
for (Index = 0; Index < Length; Index++) {
Value = PciePortRegisterRead (
Engine,
Table[Index].Reg,
Pcie
);
Value &= (~Table[Index].Mask);
Value |= Table[Index].Data;
PciePortRegisterWrite (
Engine,
Table[Index].Reg,
Value,
S3Save,
Pcie
);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Lock registers
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieLockRegisters (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS),
D0F0xE4_CORE_0010_HwInitWrLock_OFFSET,
D0F0xE4_CORE_0010_HwInitWrLock_WIDTH,
0x1,
TRUE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Exit\n");
}
/*----------------------------------------------------------------------------------------*/
/**
* Training state handling
*
*
*
* @param[in] Engine Pointer to engine config descriptor
* @param[in, out] Buffer Indicate if engine in non final state
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
STATIC
PcieUtilGlobalGenCapabilityCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIE_GLOBAL_GEN_CAP_WORKSPACE *GlobalGenCapability;
PCIE_LINK_SPEED_CAP LinkSpeedCapability;
PCIE_HOTPLUG_TYPE HotPlugType;
UINT32 Flags;
Flags = PCIE_GLOBAL_GEN_CAP_ALL_PORTS;
GlobalGenCapability = (PCIE_GLOBAL_GEN_CAP_WORKSPACE*) Buffer;
LinkSpeedCapability = PcieGen1;
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
Flags |= PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS;
}
HotPlugType = Engine->Type.Port.PortData.LinkHotplug;
if ((HotPlugType == HotplugBasic) || (HotPlugType == HotplugServer) || (HotPlugType == HotplugEnhanced)) {
Flags |= PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS;
}
if ((GlobalGenCapability->Flags & Flags) != 0) {
ASSERT ((GlobalGenCapability->Flags & (PCIE_PORT_GEN_CAP_MAX | PCIE_PORT_GEN_CAP_BOOT)) != 0);
LinkSpeedCapability = PcieFmGetLinkSpeedCap (GlobalGenCapability->Flags, Engine);
if (GlobalGenCapability->LinkSpeedCapability < LinkSpeedCapability) {
GlobalGenCapability->LinkSpeedCapability = LinkSpeedCapability;
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Determine global GEN capability
*
*
* @param[in] Flags global GEN capability flags
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
PCIE_LINK_SPEED_CAP
PcieUtilGlobalGenCapability (
IN UINT32 Flags,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIE_LINK_SPEED_CAP GlobalCapability;
PCIE_GLOBAL_GEN_CAP_WORKSPACE GlobalGenCap;
GlobalGenCap.LinkSpeedCapability = PcieGen1;
GlobalGenCap.Flags = Flags;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieUtilGlobalGenCapabilityCallback,
&GlobalGenCap,
Pcie
);
GlobalCapability = GlobalGenCap.LinkSpeedCapability;
return GlobalCapability;
}
|