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/* $NoKeywords:$ */
/**
* @file
*
* Various PCI service routines.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
*
* AMD is granting you permission to use this software (the Materials)
* pursuant to the terms and conditions of your Software License Agreement
* with AMD. This header does *NOT* give you permission to use the Materials
* or any rights under AMD's intellectual property. Your use of any portion
* of these Materials shall constitute your acceptance of those terms and
* conditions. If you do not agree to the terms and conditions of the Software
* License Agreement, please do not use any portion of these Materials.
*
* CONFIDENTIALITY: The Materials and all other information, identified as
* confidential and provided to you by AMD shall be kept confidential in
* accordance with the terms and conditions of the Software License Agreement.
*
* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE
* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
*
* AMD does not assume any responsibility for any errors which may appear in
* the Materials or any other related information provided to you by AMD, or
* result from use of the Materials or any related information.
*
* You agree that you will not reverse engineer or decompile the Materials.
*
* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
* further information, software, technical information, know-how, or show-how
* available to you. Additionally, AMD retains the right to modify the
* Materials at any time, without notice, and is not obligated to provide such
* modified Materials to you.
*
* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
* subject to the restrictions as set forth in FAR 52.227-14 and
* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the
* Government constitutes acknowledgement of AMD's proprietary rights in them.
*
* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any
* direct product thereof will be exported directly or indirectly, into any
* country prohibited by the United States Export Administration Act and the
* regulations thereunder, without the required authorization from the U.S.
* government nor will be used for any purpose prohibited by the same.
* ***************************************************************************
*
*/
#ifndef _GNBLIBPCI_H_
#define _GNBLIBPCI_H_
#define PCIE_CAP_ID 0x10
#define IOMMU_CAP_ID 0x0F
/// PCIe device type
typedef enum {
PcieDeviceEndPoint, ///< Endpoint
PcieDeviceLegacyEndPoint, ///< Legacy endpoint
PcieDeviceRootComplex = 4, ///< Root complex
PcieDeviceUpstreamPort, ///< Upstream port
PcieDeviceDownstreamPort, ///< Downstream Port
PcieDevicePcieToPcix, ///< PCIe to PCI/PCIx bridge
PcieDevicePcixToPcie, ///< PCI/PCIx to PCIe bridge
PcieNotPcieDevice = 0xff ///< unknown device
} PCIE_DEVICE_TYPE;
typedef UINT32 SCAN_STATUS;
#define SCAN_SKIP_FUNCTIONS 0x1
#define SCAN_SKIP_DEVICES 0x2
#define SCAN_SKIP_BUSES 0x4
#define SCAN_SUCCESS 0x0
// Forward declaration needed for multi-structure mutual references
AGESA_FORWARD_DECLARATION (GNB_PCI_SCAN_DATA);
typedef SCAN_STATUS (*GNB_SCAN_CALLBACK) (
IN PCI_ADDR Device,
IN OUT GNB_PCI_SCAN_DATA *ScanData
);
///Scan supporting data
struct _GNB_PCI_SCAN_DATA {
GNB_SCAN_CALLBACK GnbScanCallback; ///< Callback for each found device
AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header
};
#define PCIE_CAP_ID 0x10
#define PCIE_LINK_CAP_REGISTER 0x0C
#define PCIE_LINK_CTRL_REGISTER 0x10
#define PCIE_DEVICE_CAP_REGISTER 0x04
#define PCIE_DEVICE_CTRL_REGISTER 0x08
#define PCIE_ASPM_L1_SUPPORT_CAP BIT11
#define MAX_PAYLOAD_128 0x0 ///< Max allowed payload size 128 bytes
#define MAX_PAYLOAD_256 0x1 ///< Max allowed payload size 256 bytes
#define MAX_PAYLOAD_512 0x2 ///< Max allowed payload size 512 bytes
#define MAX_PAYLOAD_1024 0x3 ///< Max allowed payload size 1024 bytes
#define MAX_PAYLOAD_2048 0x4 ///< Max allowed payload size 2048 bytes
#define MAX_PAYLOAD_4096 0x5 ///< Max allowed payload size 4096 bytes
#define MAX_PAYLOAD 0x5 ///< Max allowed payload size according to spec is 101b (4096 bytes)
BOOLEAN
GnbLibPciIsDevicePresent (
IN UINT32 Address,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
GnbLibPciIsBridgeDevice (
IN UINT32 Address,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
GnbLibPciIsMultiFunctionDevice (
IN UINT32 Address,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
GnbLibPciIsPcieDevice (
IN UINT32 Address,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT8
GnbLibFindPciCapability (
IN UINT32 Address,
IN UINT8 CapabilityId,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
GnbLibPciScan (
IN PCI_ADDR Start,
IN PCI_ADDR End,
IN GNB_PCI_SCAN_DATA *ScanData
);
VOID
GnbLibPciScanSecondaryBus (
IN PCI_ADDR Bridge,
IN OUT GNB_PCI_SCAN_DATA *ScanData
);
PCIE_DEVICE_TYPE
GnbLibGetPcieDeviceType (
IN PCI_ADDR Device,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
GnbLibS3SaveConfigSpace (
IN UINT32 Address,
IN UINT16 StartRegisterAddress,
IN UINT16 EndRegisterAddress,
IN ACCESS_WIDTH Width,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif
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