1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
* Copyright (C) 2006,2007 AMD
* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <console/console.h>
#include "smbus.h"
#include "mcp55.h"
#define SMBUS0_IO_BASE 0x1000
#define SMBUS1_IO_BASE (0x1000 + (1 << 8))
/* Size: 0x40 */
void enable_smbus(void)
{
pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
if (dev == PCI_DEV_INVALID)
die("SMBus controller not found\n");
/* Set SMBus I/O base. */
pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);
pci_write_config32(dev, 0x24, SMBUS1_IO_BASE | 1);
/* Set SMBus I/O space enable. */
pci_write_config16(dev, 0x4, 0x01);
/* Clear any lingering errors, so the transaction will run. */
outb(inb(SMBUS0_IO_BASE + SMBHSTSTAT), SMBUS0_IO_BASE + SMBHSTSTAT);
outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);
}
int smbus_recv_byte(unsigned device)
{
return do_smbus_recv_byte(SMBUS0_IO_BASE, device);
}
int smbus_send_byte(unsigned device, unsigned char val)
{
return do_smbus_send_byte(SMBUS0_IO_BASE, device, val);
}
int smbus_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
}
int smbus_write_byte(unsigned device, unsigned address,
unsigned char val)
{
return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
}
int smbusx_recv_byte(unsigned smb_index, unsigned device)
{
return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index << 8), device);
}
int smbusx_send_byte(unsigned smb_index, unsigned device,
unsigned char val)
{
return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index << 8),
device, val);
}
int smbusx_read_byte(unsigned smb_index, unsigned device,
unsigned address)
{
return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index << 8),
device, address);
}
int smbusx_write_byte(unsigned smb_index, unsigned device,
unsigned address, unsigned char val)
{
return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index << 8),
device, address, val);
}
|
